Rex-BC Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62752 )
Change subject: soc/mediatek/common: Add halt() after triggering wdt reset ......................................................................
soc/mediatek/common: Add halt() after triggering wdt reset
It's more reasonable to halt when we trigger watchdog reset because whole system should be reset after we trigger watchdog reset.
BUG=b:222217317 TEST=build pass
Signed-off-by: Rex-BC Chen rex-bc.chen@mediatek.com Change-Id: I726ba1599841f63b37062f9ce2e04840e4f250bb --- M src/soc/mediatek/common/wdt.c 1 file changed, 13 insertions(+), 3 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/62752/1
diff --git a/src/soc/mediatek/common/wdt.c b/src/soc/mediatek/common/wdt.c index 4f8eff2..b012011 100644 --- a/src/soc/mediatek/common/wdt.c +++ b/src/soc/mediatek/common/wdt.c @@ -3,11 +3,23 @@ #include <arch/cache.h> #include <device/mmio.h> #include <console/console.h> +#include <halt.h> #include <soc/wdt.h> #include <vendorcode/google/chromeos/chromeos.h>
__weak void mtk_wdt_clr_status(void) { /* do nothing */ }
+static inline void mtk_wdt_swreset(void) +{ + printk(BIOS_INFO, "%s() called!\n", __func__); + + dcache_clean_all(); + setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); + write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); + + halt(); +} + int mtk_wdt_init(void) { uint32_t wdt_sta; @@ -31,9 +43,7 @@ * Before triggering secondary reset, clean the data cache so the logs in cbmem * console (either in SRAM or DRAM) can be flushed. */ - dcache_clean_all(); - setbits32(&mtk_wdt->wdt_mode, MTK_WDT_MODE_EXTEN | MTK_WDT_MODE_KEY); - write32(&mtk_wdt->wdt_swrst, MTK_WDT_SWRST_KEY); + mtk_wdt_swreset(); } else if (wdt_sta & MTK_WDT_STA_SW_RST) printk(BIOS_INFO, "normal software reboot\n"); else if (wdt_sta & MTK_WDT_STA_SPM_RST)