[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add GPIOs for Alder Lake SOC

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )

Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC
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Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... 
File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:

https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... 
PS2, Line 309:
> To solve this, one option would be to have an `opt-in` FSP option for pad configuration: […]

Angel, please check this https://github.com/coreboot/coreboot/blob/master/src/soc/intel/tigerlake/rom...

I'm had refer about SoC default GPIO :) not sure if i have done in mistake conveying the same where FSP also don't touch those GPIOs. ideally no one program those PADs, one could argue, what happen if i want to touch from coreboot, its okay to do i believe as long as its part of EDS, which is not the case, so if like to do randomly knowing there is GPIO COMM 3 and let configure those to NF without knowing the PIN number and description is only my concern.