[coreboot-gerrit] [S] Change in coreboot[main]: mb/google/fatcat/var/felino: Modify the felino config for probing TPM...

[Tongtong Pan (Code Review)]

Tongtong Pan has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85965?usp=email )

Change subject: mb/google/fatcat/var/felino: Modify the felino config for probing TPM I2C
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mb/google/fatcat/var/felino: Modify the felino config for probing TPM I2C

Modify the configuration to detect TPM I2C correctly.

BUG=b:388982526
TEST=abuild -v -a -x -c max -p none -t google/fatcat -b felino

Change-Id: I093c0bad181f133e601f3270de68c0848f847ccf
Signed-off-by: Tongtong Pan 
---
M src/mainboard/google/fatcat/Kconfig
M src/mainboard/google/fatcat/variants/felino/gpio.c
M src/mainboard/google/fatcat/variants/felino/overridetree.cb
3 files changed, 21 insertions(+), 7 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/85965/1

diff --git a/src/mainboard/google/fatcat/Kconfig b/src/mainboard/google/fatcat/Kconfig
index 37ba330..c5d235c 100644
--- a/src/mainboard/google/fatcat/Kconfig
+++ b/src/mainboard/google/fatcat/Kconfig
@@ -116,6 +116,7 @@
    hex
    default 0x03 if BOARD_GOOGLE_MODEL_FATCAT
    default 0x01 if BOARD_GOOGLE_FRANCKA
+	default 0x01 if BOARD_GOOGLE_FELINO

config FMDFILE
    default "src/mainboard/$(CONFIG_MAINBOARD_DIR)/chromeos-debug-fsp.fmd" if CHROMEOS && BUILDING_WITH_DEBUG_FSP
diff --git a/src/mainboard/google/fatcat/variants/felino/gpio.c b/src/mainboard/google/fatcat/variants/felino/gpio.c
index 645746f..b91350f 100644
--- a/src/mainboard/google/fatcat/variants/felino/gpio.c
+++ b/src/mainboard/google/fatcat/variants/felino/gpio.c
@@ -278,7 +278,7 @@
    /* GPP_F14:     NC */
    PAD_NC(GPP_F14, NONE),
    /* GPP_F15:     GSC_PCH_INT_ODL */
-	PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
+	PAD_CFG_GPI_APIC(GPP_F15, NONE, PLTRST, LEVEL, INVERT),
    /* GPP_F16:     NC */
    PAD_NC(GPP_F16, NONE),
    /* GPP_F17:     NC */
@@ -399,12 +399,12 @@
    /* GPP_H09:     UART0_BUF_TXD */
    PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1),

-	/* GPP_H06: I2C3_SDA_PSS */
-	PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1),
-	/* GPP_H07: I2C3_SCL_PSS */
-	PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1),
-	/* GPP_D15: SPI_TPM_INT_N */
-	PAD_CFG_GPI_APIC(GPP_D15, NONE, PLTRST, LEVEL, INVERT),
+	/* GPP_H21:     PCH_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22:     PCH_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+	/* GPP_F15: SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG),
 };

/* Pad configuration in romstage */
@@ -413,6 +413,13 @@
    PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1),
    /* GPP_C04:     GPP_C0_SMBDATA */
    PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1),
+
+	/* GPP_H21:     PCH_I2C_GSC_SDA */
+	PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
+	/* GPP_H22:     PCH_I2C_GSC_SCL */
+	PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
+	/* GPP_F15: SPI_TPM_INT_N */
+	PAD_CFG_GPI_APIC_LOCK(GPP_F15, NONE, LEVEL, INVERT, LOCK_CONFIG),
 };

const struct pad_config *variant_gpio_table(size_t *num)
diff --git a/src/mainboard/google/fatcat/variants/felino/overridetree.cb b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
index 1f3d07b..28072d5 100644
--- a/src/mainboard/google/fatcat/variants/felino/overridetree.cb
+++ b/src/mainboard/google/fatcat/variants/felino/overridetree.cb
@@ -47,6 +47,12 @@
    		[DDI_PORT_A] = DDI_ENABLE_HPD,
    }"

+	register "serial_io_i2c_mode" = "{
+		[PchSerialIoIndexI2C0]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C1]  = PchSerialIoPci,
+		[PchSerialIoIndexI2C4]  = PchSerialIoPci,
+	}"
+
    # Intel Common SoC Config
    #+-------------------+---------------------------+
    #| Field             |  Value                    |