[coreboot-gerrit] Patch merged into coreboot/master: dc7daca baytrail: print dram configuration

the following patch was just integrated into master:
commit dc7dacab84b67d5b6f4377d9045d2327d24de942
Author: Aaron Durbin 
Date:   Fri Oct 11 00:26:04 2013 -0500

baytrail: print dram configuration

After running the MRC blob print out some information
    on the training: MRC version, number channels, DDR3
    type, and DRAM frequency.

Example output:
    MRC v0.90
    2 channels of DDR3 @ 1066MHz

Apparently there are two dunit IOSF ports -- 1 for each
    channel. However, certain registers really on live in
    channel 0. Thus, there was some changes to dunit support
    in the iosf area.

BUG=chrome-os-partner:22875
    BRANCH=None
    TEST=Built and booted bayleybay in different configs.

Change-Id: Ib306432b55f9222b4eb3d14b2467bc0e7617e24f
    Signed-off-by: Aaron Durbin 
    Reviewed-on: https://chromium-review.googlesource.com/172770
    Reviewed-by: Shawn Nematbakhsh

See http://review.coreboot.org/4882 for details.

-gerrit