Attention is currently required from: Subrata Banik, Haribalaraman Ramasubramanian, Reka Norman, Rizwan Qureshi, Tim Wawrzynczak, Daniil Lunev, Nick Vaccaro, Divagar Mohandass.
Meera Ravindranath has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68251 )
Change subject: soc/intel/{adl,cmn}: Add/Remove LTR disqualification for UFS ......................................................................
Patch Set 7:
(6 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/68251/comment/6bab2266_a035939b PS1, Line 8: : a) Add LTR disqualification in D3 to ensure PMC ignores LTR : from UFS IP as it is infinite. : b) Remove LTR disqualification in _PS0 to ensure PMC stops : ignoring LTR from UFS IP during D3 exit.
"LTR ignore" is a work around from IP team. TA is pending. […]
Done
Commit Message:
https://review.coreboot.org/c/coreboot/+/68251/comment/5ce7bb9a_1bd10d99 PS6, Line 7: alderlake
{adl, cmn}
Done
Patchset:
PS1:
yes, that is why I am guessing 😊. […]
Ack
File src/soc/intel/alderlake/include/soc/ufs.h:
https://review.coreboot.org/c/coreboot/+/68251/comment/ce8111e5_e84ac132 PS6, Line 26: R_PMC_PWRM_LTR_IGN
Is this in the EDS? I can't see it.
yes it is, Chapter 13.3.89 in V2 EDS
https://review.coreboot.org/c/coreboot/+/68251/comment/c00d94fd_63c851d9 PS6, Line 27: PCH_PWRM_BASE_SIZE
This is redefining a macro from iomap.h. Should it be called something else? […]
The name suggestion came from Subrata. What would you like it to be? The region 0x1E30 indicates the offset till which we want to map the register space from the PWRM base. Ideally, anything more than 0x1B0C would do since LTR IGN is the only register we are using. But used the same offset as the reference platform code did.
File src/soc/intel/common/block/acpi/acpi/ufs.asl:
https://review.coreboot.org/c/coreboot/+/68251/comment/b0b5c16b_69c22000 PS6, Line 71: , 1
Is this field supposed to be blank?
Yes, indicates the 18th bit of LTR IGN register.