[coreboot-gerrit] Change in ...coreboot[master]: mb/google/sarien: Enable LTR for PCIe NVMe root port

[Roy Mingi Park (Code Review)]

Roy Mingi Park has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32456 )

Change subject: mb/google/sarien: Enable LTR for PCIe NVMe root port
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Patch Set 1: Code-Review+1

I verified with this CL and it became ASPM L1.2+ from ASPM_L1.2- on arcada DVT1.

Before:
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2- ASPM_L1.1+

After:
L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+