[coreboot-gerrit] Change in ...coreboot[master]: soc/amd/stoneyridge: Add ACPI D3Cold support for SD Controller

[Daniel Kurtz (Code Review)]

Daniel Kurtz has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32433 )

Change subject: soc/amd/stoneyridge: Add ACPI D3Cold support for SD Controller
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Patch Set 2:

(1 comment)

https://review.coreboot.org/#/c/32433/2/src/soc/amd/stoneyridge/acpi/sb_pci0... 
File src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl:

https://review.coreboot.org/#/c/32433/2/src/soc/amd/stoneyridge/acpi/sb_pci0... 
PS2, Line 455: 				/* D0-uninitialized */
oh, hmm. sorry I didn't catch this earlier.  It looks like, based on the "shoes-and-socks" principle, and on the other equivalent blocks above, that this next line should come first in the "D0" case.  That is, for consistency, we first clear the state bits, then actually power on.  and in the D3 case, we first disable power and then set the state bits.