Timothy Pearson (tpearson@raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14192
-gerrit
commit c7a7bff3c75989d8927162a133bdd95249f4c479 Author: Timothy Pearson tpearson@raptorengineeringinc.com Date: Wed Mar 30 13:48:24 2016 -0500
nb/amd_mct_ddr3: Move DRAM MCE sync flood enable to ramstage
Enabling sync flood on DRAM MCE directly after ECC clear can lead to a system hang with no way to determine the offending DRAM module. Clear MCEs after ECC setup, but do not enable sync flood until NB setup in ramstage to allow time for any MCEs to accumulate in the status registers. Before enabling sync flood on MCE, determine if any MCEs were logged during ramstage execution and display them on the serial console.
Change-Id: Ibd93801be2eed06d89c8d306c14aef5558dd5a15 Signed-off-by: Timothy Pearson tpearson@raptorengineeringinc.com --- src/northbridge/amd/amdfam10/misc_control.c | 45 ++++++++++++++++++++++++++ src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c | 10 ------ 2 files changed, 45 insertions(+), 10 deletions(-)
diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index d6f9fd9..2fe715c 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -30,6 +30,7 @@ #include <device/pci_ops.h> #include <pc80/mc146818rtc.h> #include <lib.h> +#include <cbmem.h> #include <cpu/amd/model_10xxx_rev.h>
#include "amdfam10.h" @@ -152,6 +153,50 @@ static void misc_control_init(struct device *dev)
printk(BIOS_DEBUG, "NB: Function 3 Misc Control.. ");
+#if IS_ENABLED(CONFIG_DIMM_DDR3) && !IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_AGESA) + uint8_t node; + uint8_t slot; + uint8_t dimm_present; + + /* Restore DRAM MCA registers */ + struct amdmct_memory_info *mem_info; + mem_info = cbmem_find(CBMEM_ID_AMDMCT_MEMINFO); + if (mem_info) { + node = PCI_SLOT(dev->path.pci.devfn) - 0x18; + + /* Check node for installed DIMMs */ + dimm_present = 0; + + /* Check all slots for installed DIMMs */ + for (slot = 0; slot < MAX_DIMMS_SUPPORTED; slot++) { + if (mem_info->dct_stat[node].DIMMPresent & (1 << slot)) { + dimm_present = 1; + break; + } + } + + if (dimm_present) { + uint32_t mc4_status_high = pci_read_config32(dev, 0x4c); + uint32_t mc4_status_low = pci_read_config32(dev, 0x48); + if (mc4_status_high != 0) { + printk(BIOS_WARNING, "\nWARNING: MC4 Machine Check Exception detected on node %d!\n" + "Signature: %08x%08x\n", node, mc4_status_high, mc4_status_low); + } + + /* Clear MC4 error status */ + pci_write_config32(dev, 0x48, 0x0); + pci_write_config32(dev, 0x4c, 0x0); + + if (mem_info->dct_stat[node].mca_config_backed_up) { + dword = pci_read_config32(dev, 0x44); + dword |= (mem_info->dct_stat[node].sync_flood_on_dram_err & 0x1) << 30; + dword |= (mem_info->dct_stat[node].sync_flood_on_any_uc_err & 0x1) << 21; + pci_write_config32(dev, 0x44, dword); + } + } + } +#endif + /* Disable Machine checks from Invalid Locations. * This is needed for PC backwards compatibility. */ diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c index 07eb0bd..1077cb8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctecc_d.c @@ -84,8 +84,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) u32 val; u16 nvbits;
- uint32_t dword; - mctHookBeforeECC();
/* Construct these booleans, based on setup options, for easy handling @@ -266,14 +264,6 @@ u8 ECCInit_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstatA) /* Clear MC4 error status */ pci_write_config32(pDCTstat->dev_nbmisc, 0x48, 0x0); pci_write_config32(pDCTstat->dev_nbmisc, 0x4c, 0x0); - - /* Restore previous MCA error handling settings */ - if (pDCTstat->mca_config_backed_up) { - dword = Get_NB32(pDCTstat->dev_nbmisc, 0x44); - dword |= (pDCTstat->sync_flood_on_dram_err & 0x1) << 30; - dword |= (pDCTstat->sync_flood_on_any_uc_err & 0x1) << 21; - Set_NB32(pDCTstat->dev_nbmisc, 0x44, dword); - } } } }