[coreboot-gerrit] Change in coreboot[master]: soc/intel/jasperlake: Allow devicetree to fill Emmc tuning params

[Maulik V Vaghela (Code Review)]

Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/46872 )

Change subject: soc/intel/jasperlake: Allow devicetree to fill Emmc tuning params
......................................................................

soc/intel/jasperlake: Allow devicetree to fill Emmc tuning params

JasperLake FSP provides an option to pass custom dll tuning upd values
to be filled from coreboot. Coreboot was not using this parameters till
now. With new EMMC devices being used, we may need to tune dll settings
of EMMC.

This patch enables developer or OEM to fill in custom dll tuning values
via devicetree of respective board.

Emmc tuning params customization through devicetree was already available
for previous Intel SoCs, porting this feature for Jasperlake.

BUG=None
BRANCH=None
TEST=Compilation succeeds and jslrvp boots fine with this patch

Change-Id: I69940faa5ffd2c8f5532cea5c9b185cede1bf1b3
Signed-off-by: Maulik V Vaghela 
---
M src/soc/intel/jasperlake/chip.h
M src/soc/intel/jasperlake/fsp_params.c
2 files changed, 32 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/46872/1

diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index 5e90530..624541a 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -125,6 +125,20 @@

/* eMMC and SD */
    uint8_t ScsEmmcHs400Enabled;
+	/* Set if FSP should use HS400 DLL values from policy */
+	uint8_t ScsEmmcUseCustomDlls;
+	/* Emmc Tx CMD Delay control register value */
+	uint32_t ScsEmmcTxCmdDelayRegValue;
+	/* Emmc Tx DATA Delay control 1 register value */
+	uint32_t ScsEmmcTxDataDelay1RegValue;
+	/* Emmc Tx DATA Delay control 2 register value */
+	uint32_t ScsEmmcTxDataDelay2RegValue;
+	/* Emmc Rx CMD + DATA Delay control 1 register value */
+	uint32_t ScsEmmcRxCmdDataDelay1RegValue;
+	/* Emmc Rx CMD + DATA Delay control 2 register value */
+	uint32_t ScsEmmcRxCmdDataDelay2RegValue;
+	/* Emmc Rx Strobe Delay control register value */
+	uint32_t ScsEmmcRxStrobeDelayRegValue;

/* Enable if SD Card Power Enable Signal is Active High */
    uint8_t SdCardPowerEnableActiveHigh;
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index db27234..67aa6db 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -199,8 +199,25 @@
    /* eMMC configuration */
    dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
    params->ScsEmmcEnabled = is_dev_enabled(dev);
-	if (params->ScsEmmcEnabled)
+	if (params->ScsEmmcEnabled) {
    	params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled;
+		params->EmmcUseCustomDlls = config->ScsEmmcUseCustomDlls;
+		/* Emmc custom Dll tuning parameters */
+		if (config->ScsEmmcUseCustomDlls) {
+			params->EmmcTxCmdDelayRegValue = \
+						config->ScsEmmcTxCmdDelayRegValue;
+			params->EmmcTxDataDelay1RegValue = \
+						config->ScsEmmcTxDataDelay1RegValue;
+			params->EmmcTxDataDelay2RegValue = \
+						config->ScsEmmcTxDataDelay2RegValue;
+			params->EmmcRxCmdDataDelay1RegValue = \
+						config->ScsEmmcRxCmdDataDelay1RegValue;
+			params->EmmcRxCmdDataDelay2RegValue = \
+						config->ScsEmmcRxCmdDataDelay2RegValue;
+			params->EmmcRxStrobeDelayRegValue = \
+						config->ScsEmmcRxStrobeDelayRegValue;
+		}
+	}

/* Enable xDCI controller if enabled in devicetree and allowed */
    dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);