[coreboot-gerrit] [XS] Change in coreboot[master]: mtl: Allow call to cse_fw_sync() in romstage when SPLIT_FW_SYNC selected

[Krishna P Bhat D (Code Review)]

Attention is currently required from: Kapil Porwal, Subrata Banik, Tarun Tuli.

Krishna P Bhat D has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/75603?usp=email )

Change subject: mtl: Allow call to cse_fw_sync() in romstage when SPLIT_FW_SYNC selected
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mtl: Allow call to cse_fw_sync() in romstage when SPLIT_FW_SYNC selected

When split CSE firmware update option is chosen, allow call to
cse_fw_sync() in romstage. In romstage, the decision to switch to RW
from RO is made.

Change-Id: I68c706bd4d53a768d1a5011b9dff441fee8f9e1f
Signed-off-by: Krishna Prasad Bhat 
---
M src/soc/intel/meteorlake/romstage/romstage.c
1 file changed, 2 insertions(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/03/75603/1

diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c
index b5351de..a6a281b 100644
--- a/src/soc/intel/meteorlake/romstage/romstage.c
+++ b/src/soc/intel/meteorlake/romstage/romstage.c
@@ -128,7 +128,8 @@
    /* Initialize HECI interface */
    cse_init(HECI1_BASE_ADDRESS);

-	if (!s3wake && CONFIG(SOC_INTEL_CSE_LITE_SKU))
+	if (!s3wake && (CONFIG(SOC_INTEL_CSE_LITE_SKU) ||
+		CONFIG(SOC_INTEL_CSE_LITE_SPLIT_FW_SYNC)))
    	cse_fw_sync();

/* Update coreboot timestamp table with CSE timestamps */