[coreboot-gerrit] Change in coreboot[master]: soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE

[Angel Pons (Code Review)]

Angel Pons has submitted this change. ( https://review.coreboot.org/c/coreboot/+/43982 )

Change subject: soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE
......................................................................

soc/intel/xeon_sp/cpx: configure DIMM_MAX and DIMM_SPD_SIZE

CPX-SP processor has 2 IMC, there are 3 channels per IMC,
2 DIMMs per channel.

It supports DDR4.

Configure default values for DIMM_MAX and DIMM_SPD_SIZE accordingly.

Change-Id: I66cc512465362d5ba04dc36534360c94ca23e77a
Signed-off-by: Jonathan Zhang 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43982
Reviewed-by: Angel Pons 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/xeon_sp/cpx/Kconfig
1 file changed, 11 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Angel Pons: Looks good to me, approved

diff --git a/src/soc/intel/xeon_sp/cpx/Kconfig b/src/soc/intel/xeon_sp/cpx/Kconfig
index 9c6450e..bd1fa97 100644
--- a/src/soc/intel/xeon_sp/cpx/Kconfig
+++ b/src/soc/intel/xeon_sp/cpx/Kconfig
@@ -68,4 +68,15 @@

select CACHE_MRC_SETTINGS

+# CPX-SP has 2 IMCs, 3 channels per IMC, 2 DIMMs per channel
+# Default value is set to one socket, full config.
+config DIMM_MAX
+	int
+	default 12
+
+# DDR4
+config DIMM_SPD_SIZE
+	int
+	default 512
+
 endif