Patrick Georgi (pgeorgi@google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13835
-gerrit
commit 5b67a3324ac5e229542709fa6a05c4b29492cca5 Author: Subrata Banik subrata.banik@intel.com Date: Mon Feb 8 17:15:29 2016 +0530
Skylake: Support Intel Speed Shift Technology based on config
Intel Speed Shift Technology is a new mechanism that replaces Legacy P-state. ISST allows OS hints about energy/performance preference. H/W performs the actual P-state control (autonomous)
1. Optimization frequency seclection for low residency workloads, no longer a static knee point. 2. Optimized frequency selection for best energy to performance trade offs. 3. Kick down frequency (from idle) fpr best responsiveness while taking energy consumption init account.
Coreboot's responsiblity is to configure MSR 0x1AA ISST_EN bits which will reflect in CPUID.06h:EAX[Bit 7] that driver checkes and enable HWP accordingly.
BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu and verify HWP getting enabled/disabled using Intel P-state driver.
Change-Id: I91722aa1077f4ef6c8620b103be3e29cfcd974e5 Signed-off-by: Patrick Georgi pgeorgi@google.com Original-Commit-Id: aa7d004cb2e19047e4434e3e2544cf69393ce28f Original-Change-Id: Ie617da337babde7f196a7af712263e37f7eed56f Original-Signed-off-by: Robbie Zhang robbie.zhang@intel.com Original-Signed-off-by: Subrata Banik subrata.banik@intel.com Original-Reviewed-on: https://chromium-review.googlesource.com/313107 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org Original-Reviewed-by: Wenkai Du wenkai.du@intel.com --- src/soc/intel/skylake/chip.h | 2 ++ src/soc/intel/skylake/cpu.c | 29 +++++++++++++++++++++++++++++ src/soc/intel/skylake/include/soc/msr.h | 3 +++ 3 files changed, 34 insertions(+)
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 0b87f2d..6203916 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -326,6 +326,8 @@ struct soc_intel_skylake_config { /* PL2 Override value in Watts */ u32 tdp_pl2_override; u8 PmTimerDisabled; + /* Intel Speed Shift Technology */ + u8 speed_shift_enable; };
typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 2fa8582..327bee9 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -207,6 +207,32 @@ static void configure_thermal_target(void) } }
+static void configure_isst(void) +{ + device_t dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; + msr_t msr; + + if (conf->speed_shift_enable) { + /* + * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP + is supported or not. Coreboot needs to configure MSR 0x1AA + which is then reflected in the CPUID register. + */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } else { + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } +} + static void configure_misc(void) { msr_t msr; @@ -335,6 +361,9 @@ static void cpu_core_init(device_t cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc();
+ /* Configure Intel Speed Shift */ + configure_isst(); + /* Thermal throttle activation offset */ configure_thermal_target();
diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index db154b7..4d295e1 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -36,6 +36,9 @@ #define IA32_MISC_ENABLE 0x1a0 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MISC_PWR_MGMT_ISST_EN (1 << 6) +#define MISC_PWR_MGMT_ISST_EN_INT (1 << 7) +#define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_PERF_CTL 0x199