Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34805 )
Change subject: arch/x86: Add postcar_frame_add_top_of_ram_cache() API ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/34805/1/src/arch/x86/postcar_loader... File src/arch/x86/postcar_loader.c:
https://review.coreboot.org/c/coreboot/+/34805/1/src/arch/x86/postcar_loader... PS1, Line 135: MTRR_TYPE_WRPROT
0x00000000fef00006: PHYBASE0: Address = 0x00000000fef00000, WB
That's just CAR region. That has nothing to do with the DRAM address regions. I can't claim to understand the issue you are seeing since there should be no overlapping regions being set. I'm not sure what system you are running on or what type of CAR implementation is being used. Yes, if you set a region that will be used as cacheable and nothing is enabled to ensure no eviction of CAR data lines then things will indeed break.
If the CAR implementation is reliant upon software not over expending the cache size then one can't do this. If it's a full implementation that ensures no eviction then it wouldn't be a problem.