[coreboot-gerrit] [S] Change in coreboot[main]: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIRs

[Name of user not set (Code Review)]

Attention is currently required from: Shuo Liu.

Hello Shuo Liu,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/85012?usp=email

to look at the new patch set (#2).

Change subject: soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIRs
......................................................................

soc/intel/common/block/itss: Route PCI INT pin to PIRQ using PIRs

ITSS has PCI Interrupt Route (PIR) registers to map PCI INTA-D to one
of PIRQA-H. This patch adds a funtion `itss_get_dev_pirq()` returning
PIRQ for a given device and INT pin.

Change-Id: If911b34c506a4a3657b873baab33814c1a7d674b
Signed-off-by: Yuchi Chen 
---
M src/soc/intel/common/block/include/intelblocks/itss.h
M src/soc/intel/common/block/itss/itss.c
2 files changed, 19 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/85012/2