Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/87114?usp=email )
Change subject: drivers/smmstore: Support 64-bit MMIO addresses ......................................................................
drivers/smmstore: Support 64-bit MMIO addresses
Currently the SMMSTOREv2 only support MMIO ROM below 4GiB. As the space below 4GiB is typically limited on x86, add support for extended MMIO ROM windows as found on recent hardware. Allow the SMMSTOREv2 to be memory mapped above 4GiB by adding a new field to the coreboot table called 'mmap_addr_high'. The users outside of coreboot must check the size field of the coreboot struct to determine if mmap_addr_high is supported. When it is it holds the 64-bit physical address to the MMIO ROM window.
Change-Id: I1131cfa5cdbf92bbd33de3e5b22a305136eec9f7 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M Documentation/drivers/smmstorev2.md M src/commonlib/include/commonlib/coreboot_tables.h M src/drivers/smmstore/ramstage.c M src/include/smmstore.h 4 files changed, 25 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/87114/1
diff --git a/Documentation/drivers/smmstorev2.md b/Documentation/drivers/smmstorev2.md index af6e0ce..2e9f38f 100644 --- a/Documentation/drivers/smmstorev2.md +++ b/Documentation/drivers/smmstorev2.md @@ -74,19 +74,26 @@ struct lb_smmstorev2 { uint32_t tag; uint32_t size; - uint32_t num_blocks; /* Number of writeable blocks in SMM */ - uint32_t block_size; /* Size of a block in byte. Default: 64 KiB */ - uint32_t mmap_addr; /* MMIO address of the store for read only access */ - uint32_t com_buffer; /* Physical address of the communication buffer */ - uint32_t com_buffer_size; /* Size of the communication buffer in byte */ - uint8_t apm_cmd; /* The command byte to write to the APM I/O port */ - uint8_t unused[3]; /* Set to zero */ + uint32_t num_blocks; /* Number of writable blocks in SMM */ + uint32_t block_size; /* Size of a block in byte. Default: 64 KiB */ + uint32_t mmap_addr; /* MMIO address of the store for read only access. + When set to zero the address is set in mmap_addr_high. */ + uint32_t com_buffer; /* Physical address of the communication buffer */ + uint32_t com_buffer_size; /* Size of the communication buffer in bytes */ + uint8_t apm_cmd; /* The command byte to write to the APM I/O port */ + uint8_t unused[3]; /* Set to zero */ + uint64_t mmap_addr_high; /* When the ROM MMIO address is above 4GiB the 'mmap_addr' cannot hold it. + In that case 'mmap_addr' is cleared and the address to the ROM MMIO is + passed here. (Optional) */ }; ```
The absence of this coreboot table entry indicates that there's no SMMSTOREv2 support.
+`mmap_addr_high` is an optional field added after the initial implementation. +Users of this table must check the size field to know if it's written by coreboot. +In case it's not present the SPI ROM MMIO address must be below 4 GiB. ### Blocks
The SMMSTOREv2 splits the SMMSTORE FMAP partition into smaller chunks diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 78dbe8e..c0cfa39 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -539,11 +539,15 @@ uint32_t size; uint32_t num_blocks; /* Number of writable blocks in SMM */ uint32_t block_size; /* Size of a block in byte. Default: 64 KiB */ - uint32_t mmap_addr; /* MMIO address of the store for read only access */ + uint32_t mmap_addr; /* MMIO address of the store for read only access. + When set to zero the address is set in mmap_addr_high. */ uint32_t com_buffer; /* Physical address of the communication buffer */ uint32_t com_buffer_size; /* Size of the communication buffer in bytes */ uint8_t apm_cmd; /* The command byte to write to the APM I/O port */ uint8_t unused[3]; /* Set to zero */ + uint64_t mmap_addr_high; /* When the ROM MMIO address is above 4GiB the 'mmap_addr' cannot hold it. + In that case 'mmap_addr' is cleared and the address to the ROM MMIO is + passed here. (Added after initial implementation) */ };
enum lb_tpm_ppi_tpm_version { diff --git a/src/drivers/smmstore/ramstage.c b/src/drivers/smmstore/ramstage.c index 1cbf9fb..85dfff2 100644 --- a/src/drivers/smmstore/ramstage.c +++ b/src/drivers/smmstore/ramstage.c @@ -28,7 +28,11 @@ store->size = sizeof(*store); store->com_buffer = (uintptr_t)cbmem_entry_start(e); store->com_buffer_size = cbmem_entry_size(e); - store->mmap_addr = info.mmap_addr; + if (info.mmap_addr < 4ULL * GiB) + store->mmap_addr = info.mmap_addr; + else + store->mmap_addr = 0; + store->mmap_addr_high = info.mmap_addr; store->num_blocks = info.num_blocks; store->block_size = info.block_size; store->apm_cmd = APM_CNT_SMMSTORE; diff --git a/src/include/smmstore.h b/src/include/smmstore.h index 6805cbc..ef7bd1f 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -59,7 +59,7 @@ struct smmstore_params_info { uint32_t num_blocks; uint32_t block_size; - uint32_t mmap_addr; + uint64_t mmap_addr; } __packed;
/*