Attention is currently required from: Subrata Banik, Wonkyu Kim, Ravishankar Sarawadi, Nick Vaccaro, Tim Wawrzynczak.
Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/63471 )
Change subject: soc/intel/cmn/{block, pch}: Migrate GPMR driver
......................................................................
Patch Set 13:
(3 comments)
File src/soc/intel/common/block/lpc/lpc_lib.c:
https://review.coreboot.org/c/coreboot/+/63471/comment/9bec7bb5_32afd57d
PS13, Line 29: gpmr_write32
This write was changed from 16 bits to 32 bits, is it OK?
https://review.coreboot.org/c/coreboot/+/63471/comment/81258ea1_192f8096
PS13, Line 47: gpmr_write32
Ditto.
File src/soc/intel/common/pch/lockdown/lockdown.c:
https://review.coreboot.org/c/coreboot/+/63471/comment/5c124065_cc07d821
PS13, Line 40: gpmr_or32(GPMR_GCS, GPMR_GCS_BILD);
:
: /*
: * Set Secure Register Lock (SRL) bit in DMI control register to lock
: * DMI configuration.
: */
: gpmr_or32(GPMR_DMICTL, GPMR_DMICTL_SRLOCK);
Does MTL have these registers in MCHBAR?
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