Attention is currently required from: Subrata Banik. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 8:
(2 comments)
File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/comment/764db002_b475874c PS8, Line 10: /* GPIO COMM 0 */ : #define GPP_B 0x0 : #define GPP_T 0x1 : #define GPP_A 0x2 : /* GPIO COMM 1 */ : #define GPP_S 0x3 : #define GPP_H 0x4 : #define GPP_D 0x5 : /* GPIO COMM 2 */ : #define GPD 0x6 : /* GPIO COMM 4 */ : #define GPP_C 0x7 : #define GPP_F 0x8 : #define GPP_HVMOS 0x9 : #define GPP_E 0xA : /* GPIO COMM 5 */ : #define GPP_R 0xB : #define GPP_SPI0 0xC : These are wrong. They do not match PCH EDS Vol 2 v1.0.
File src/soc/intel/alderlake/include/soc/pmc.h:
https://review.coreboot.org/c/coreboot/+/45571/comment/f0fb61dc_b8c290f7 PS8, Line 128: : #define PMC_GPP_B 0x0 : #define PMC_GPP_T 0x1 : #define PMC_GPP_A 0x2 : #define PMC_GPP_S 0x3 : #define PMC_GPP_H 0x4 : #define PMC_GPP_D 0x5 : #define PMC_GPD 0x6 : #define PMC_GPP_C 0x7 : #define PMC_GPP_F 0x8 : #define PMC_GPP_HVMOS 0x9 : #define PMC_GPP_E 0xA : #define PMC_GPP_R 0xB : #define PMC_GPP_SPI0 0xC These are wrong. They do not match PCH EDS Vol 2 v1.0.