Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3584
-gerrit
commit 248979a18abed70a1a82d802ffc4ba595b474ad5 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Mon Jul 1 11:21:53 2013 +0300
intel/i945: Use MMCONF_SUPPORT_DEFAULT
Change all PCI configuration accesses to MMIO on all boards with i945 chipset. To enable MMIO style access, add explicit PCI IO config write in the bootblock.
Change-Id: Ia1ab73f1a2dcda87db4eb9b2ffddc6f7b4382b01 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/mainboard/getac/p470/Kconfig | 1 - src/mainboard/ibase/mb899/Kconfig | 1 - src/mainboard/intel/d945gclf/Kconfig | 1 - src/mainboard/kontron/986lcd-m/Kconfig | 1 - src/mainboard/lenovo/t60/Kconfig | 1 - src/mainboard/lenovo/x60/Kconfig | 1 - src/mainboard/roda/rk886ex/Kconfig | 1 - src/northbridge/intel/i945/Kconfig | 6 ++++++ src/northbridge/intel/i945/bootblock.c | 24 ++++++++++++++++++++++++ src/northbridge/intel/i945/early_init.c | 1 - 10 files changed, 30 insertions(+), 8 deletions(-)
diff --git a/src/mainboard/getac/p470/Kconfig b/src/mainboard/getac/p470/Kconfig index e7f3c95..3fdf6f7 100644 --- a/src/mainboard/getac/p470/Kconfig +++ b/src/mainboard/getac/p470/Kconfig @@ -36,7 +36,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select HAVE_ACPI_SLIC - select MMCONF_SUPPORT select UDELAY_LAPIC select BOARD_ROMSIZE_KB_1024 select GFXUMA diff --git a/src/mainboard/ibase/mb899/Kconfig b/src/mainboard/ibase/mb899/Kconfig index 6b3bdfa..36353b3 100644 --- a/src/mainboard/ibase/mb899/Kconfig +++ b/src/mainboard/ibase/mb899/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select BOARD_ROMSIZE_KB_512 select GFXUMA select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/intel/d945gclf/Kconfig b/src/mainboard/intel/d945gclf/Kconfig index cc9ceb5..0a9de1a 100644 --- a/src/mainboard/intel/d945gclf/Kconfig +++ b/src/mainboard/intel/d945gclf/Kconfig @@ -32,7 +32,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select BOARD_ROMSIZE_KB_512 select GFXUMA select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/kontron/986lcd-m/Kconfig b/src/mainboard/kontron/986lcd-m/Kconfig index 0dd28da..e8b7225 100644 --- a/src/mainboard/kontron/986lcd-m/Kconfig +++ b/src/mainboard/kontron/986lcd-m/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select BOARD_ROMSIZE_KB_1024 select GFXUMA select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/lenovo/t60/Kconfig b/src/mainboard/lenovo/t60/Kconfig index 952004b..bf24db7 100644 --- a/src/mainboard/lenovo/t60/Kconfig +++ b/src/mainboard/lenovo/t60/Kconfig @@ -16,7 +16,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select MMCONF_SUPPORT select GFXUMA select BOARD_ROMSIZE_KB_2048 select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/lenovo/x60/Kconfig b/src/mainboard/lenovo/x60/Kconfig index 5ecad2f..bcf5e04 100644 --- a/src/mainboard/lenovo/x60/Kconfig +++ b/src/mainboard/lenovo/x60/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select MMCONF_SUPPORT select GFXUMA select BOARD_ROMSIZE_KB_2048 select CHANNEL_XOR_RANDOMIZATION diff --git a/src/mainboard/roda/rk886ex/Kconfig b/src/mainboard/roda/rk886ex/Kconfig index 84a8543..2113deb 100644 --- a/src/mainboard/roda/rk886ex/Kconfig +++ b/src/mainboard/roda/rk886ex/Kconfig @@ -14,7 +14,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE - select MMCONF_SUPPORT select HAVE_ACPI_TABLES select HAVE_ACPI_RESUME select BOARD_ROMSIZE_KB_1024 diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index fbc9988..135cbe3 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -24,6 +24,8 @@ if NORTHBRIDGE_INTEL_I945
config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y + select MMCONF_SUPPORT + select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP select LAPIC_MONOTONIC_TIMER
@@ -32,6 +34,10 @@ config NORTHBRIDGE_INTEL_SUBTYPE_I945GC config NORTHBRIDGE_INTEL_SUBTYPE_I945GM def_bool n
+config BOOTBLOCK_NORTHBRIDGE_INIT + string + default "northbridge/intel/i945/bootblock.c" + config VGA_BIOS_ID string default "8086,27a2" diff --git a/src/northbridge/intel/i945/bootblock.c b/src/northbridge/intel/i945/bootblock.c new file mode 100644 index 0000000..4571446 --- /dev/null +++ b/src/northbridge/intel/i945/bootblock.c @@ -0,0 +1,24 @@ +#include <arch/io.h> + +/* Just re-define this instead of including i945.h. It blows up romcc. */ +#define PCIEXBAR 0x48 + +static void bootblock_northbridge_init(void) +{ + uint32_t reg; + + /* + * The "io" variant of the config access is explicitly used to + * setup the PCIEXBAR because CONFIG_MMCONF_SUPPORT_DEFAULT is set to + * to true. That way all subsequent non-explicit config accesses use + * MCFG. This code also assumes that bootblock_northbridge_init() is + * the first thing called in the non-asm boot block code. The final + * assumption is that no assembly code is using the + * CONFIG_MMCONF_SUPPORT_DEFAULT option to do PCI config acceses. + * + * The PCIEXBAR is assumed to live in the memory mapped IO space under + * 4GiB. + */ + reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */ + pci_io_write_config32(PCI_DEV(0,0,0), PCIEXBAR, reg); +} diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index d91930f..fd9f6b7 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -173,7 +173,6 @@ static void i945_setup_bars(void) /* Set up all hardcoded northbridge BARs */ pci_write_config32(PCI_DEV(0, 0x00, 0), EPBAR, DEFAULT_EPBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), MCHBAR, DEFAULT_MCHBAR | 1); - pci_write_config32(PCI_DEV(0, 0x00, 0), PCIEXBAR, DEFAULT_PCIEXBAR | 5); /* 64MB - busses 0-63 */ pci_write_config32(PCI_DEV(0, 0x00, 0), DMIBAR, DEFAULT_DMIBAR | 1); pci_write_config32(PCI_DEV(0, 0x00, 0), X60BAR, DEFAULT_X60BAR | 1);