Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45337 )
Change subject: soc/intel/{adl,apl,cnl,ehl,icl,jsl,skl,tgl}: Make use of common reset code block ......................................................................
Patch Set 5:
Patch Set 5:
Patch Set 5:
Patch Set 5:
Patch Set 5:
Patch Set 5:
Patch Set 5:
> Patch Set 5: > > > Patch Set 5: > > > > @Matt: If you could help me to get this validated quickly on SKL platform > > @Werner: Possible to check on APL platform > > > > I don't have SKL and APL connected remotely in current situation hence i'm working to enable those board for remote test setup. Your help might unblock this. > > Hey Subrata. > We will have a look at this patch and give it a try on one of our APL-mainboard. I will provide feedback in a few hours. Is a successful boot enough or should I take a closer look to something special?
Hi Subrata, I have tested your patches on mc_apl5. do_global_reset() does not work at all times. During mainboard_init() the HECI device is not available.
Log output: HECI: Global Reset(Type:1) Command BUG: me_read_config32 requests hidden 00:0f.0 PCI: dev is NULL!
In romstage and in mainboard_final (ramstage) the global reset works well.
Thanks a lot for your help. global reset is expected to work post romstage (DRAM initialization been done) somehow we might need to guard the global reset to ensure its not called from verstage or bootblock.
@Furquan, i might need to remove "reset.c" from verstage in https://review.coreboot.org/c/coreboot/+/45336/5/src/soc/intel/common/block/... / do you agree based on Mario's observation that "In romstage and in mainboard_final (ramstage) the global reset works well."
And it seems like the HECI interface is involved in do_global_reset(). Do you have in mind that there are places in coreboot where the HECI interface might be hidden? Is there a check needed to make sure HECI is reachable?
yes Werner, we have this check here https://review.coreboot.org/c/coreboot/+/45341/7/src/soc/intel/common/block/... inside cse_request_reset() to ensure HECI is enable but it doesn't check if BAR is been implemented
i guess call prior to heci_init() is key here. which is getting caleld from romstage.c
Currently heci_init() is not called for APL into romstage. I have called the function for test, but it does not change the global reset behavior during mainboard_init().