Wonkyu Kim has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37781 )
Change subject: soc/intel/tigerlake: Update ACPI files ......................................................................
Patch Set 3:
(10 comments)
https://review.coreboot.org/c/coreboot/+/37781/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/northbridge.asl:
https://review.coreboot.org/c/coreboot/+/37781/2/src/soc/intel/tigerlake/acp... PS2, Line 311: F Recent merged patch has fix for this address
https://review.coreboot.org/c/coreboot/+/37781/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/norththbridge.asl:
https://review.coreboot.org/c/coreboot/+/37781/2/src/soc/intel/tigerlake/acp... PS2, Line 1: /* : * This file is part of the coreboot project. : * : * Copyright (C) 2019 Intel Corp. : * : * This program is free software; you can redistribute it and/or modify : * it under the terms of the GNU General Public License as published by : * the Free Software Foundation; either version 2 of the License, or : * (at your option) any later version. : * : * This program is distributed in the hope that it will be useful, : * but WITHOUT ANY WARRANTY; without even the implied warranty of : * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the : * GNU General Public License for more details. : */ Delete this file
https://review.coreboot.org/c/coreboot/+/37781/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/pch_clock_ctl.asl:
https://review.coreboot.org/c/coreboot/+/37781/2/src/soc/intel/tigerlake/acp... PS2, Line 25: // Use C stlye comments like other ASL
https://review.coreboot.org/c/coreboot/+/37781/2/src/soc/intel/tigerlake/acp... PS2, Line 42: // : // Number Of Clocks : // Use C stlye comments like other ASL
https://review.coreboot.org/c/coreboot/+/37781/2/src/soc/intel/tigerlake/acp... PS2, Line 56: // : // Arg0 - Clock number (0:IMGCLKOUT_0, etc) : // Arg1 - Desired state (0:Disable, 1:Enable) : // Use C stlye comments like other ASL
https://review.coreboot.org/c/coreboot/+/37781/2/src/soc/intel/tigerlake/acp... PS2, Line 95: // : // Clock Frequency : // Use C stlye comments like other ASL
https://review.coreboot.org/c/coreboot/+/37781/2/src/soc/intel/tigerlake/acp... PS2, Line 100: // : // Arg0 - Clock number (0:IMGCLKOUT_0, etc) : // Arg1 - Clock frequency (0:24MHz, 1:19.2MHz) : / Use C stlye comments like other ASL
https://review.coreboot.org/c/coreboot/+/37781/2/src/soc/intel/tigerlake/acp... PS2, Line 139: //---------------------------------------------------------------------------------------- : // Clock control Method : // Arg0: Clock source select (0: IMGCLKOUT_0, 1: IMGCLKOUT_1, 2: IMGCLKOUT_2, 3: IMGCLKOUT_3, 4: IMGCLKOUT_4) : // Arg1: Clock Enable / Disable (0: Disable, 1: Enable) : // Arg2: Select 24MHz / 19.2 MHz (0: 24MHz, 1: 19.2MHz : //--------------------------------------------------------------------------------------- Use C stlye comments like other ASL
https://review.coreboot.org/c/coreboot/+/37781/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/pcie.asl:
https://review.coreboot.org/c/coreboot/+/37781/2/src/soc/intel/tigerlake/acp... PS2, Line 384: Device (TBT1) : { : Name (_ADR, 0x001D0008) : : OperationRegion (RPCS, PCI_Config, 0x4c, 4) : Field (RPCS, AnyAcc, NoLock, Preserve) : { : , 24, : RPPN, 8, /* Root Port Number */ : } : : Method (_PRT) : { : Return (IRQM (RPPN)) : } : } : : Device (TBT2) : { : Name (_ADR, 0x001D0009) : : OperationRegion (RPCS, PCI_Config, 0x4c, 4) : Field (RPCS, AnyAcc, NoLock, Preserve) : { : , 24, : RPPN, 8, /* Root Port Number */ : } : : Method (_PRT) : { : Return (IRQM (RPPN)) : } : } : : Device (TBT3) : { : Name (_ADR, 0x001D000A) : : OperationRegion (RPCS, PCI_Config, 0x4c, 4) : Field (RPCS, AnyAcc, NoLock, Preserve) : { : , 24, : RPPN, 8, /* Root Port Number */ : } : : Method (_PRT) : { : Return (IRQM (RPPN)) : } : } : : Device (TBT4) : { : Name (_ADR, 0x001D000B) : : OperationRegion (RPCS, PCI_Config, 0x4c, 4) : Field (RPCS, AnyAcc, NoLock, Preserve) : { : , 24, : RPPN, 8, /* Root Port Number */ : } : : Method (_PRT) : { : Return (IRQM (RPPN)) : } : } : Remove
https://review.coreboot.org/c/coreboot/+/37781/2/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/pmc.asl:
https://review.coreboot.org/c/coreboot/+/37781/2/src/soc/intel/tigerlake/acp... PS2, Line 17: // Intel PMC Controller 0:1f.2 C sytle comments