Edward O'Callaghan (eocallaghan@alterapraxis.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7616
-gerrit
commit 0739cbf69b44b77238df34e41ea5d5a0fc27079e Author: Edward O'Callaghan eocallaghan@alterapraxis.com Date: Mon Dec 1 03:37:04 2014 +1100
cpu/amd/agesa/family15rl/model_15_init.c: Enable TopologyExtensions
Change-Id: Ifaad4c3e9be01fa27956ea0c9efb9beddda4a6d2 Signed-off-by: Edward O'Callaghan eocallaghan@alterapraxis.com --- src/cpu/amd/agesa/family15rl/model_15_init.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/src/cpu/amd/agesa/family15rl/model_15_init.c b/src/cpu/amd/agesa/family15rl/model_15_init.c index 5cf78d1..dc6d748 100644 --- a/src/cpu/amd/agesa/family15rl/model_15_init.c +++ b/src/cpu/amd/agesa/family15rl/model_15_init.c @@ -103,6 +103,18 @@ static void model_15_init(device_t dev) printk(BIOS_DEBUG, "siblings = %02d, ", siblings); #endif
+ /* Enable TopologyExtensions */ + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + uint64_t msr_bit54 = BIT_64(54); + msr.lo |= msr_bit54 >> 32; + msr.hi |= msr_bit54 & 32; + wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); + msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); + if (msr.lo & (msr_bit54 >> 32)) { + cpu_idx = cpu_info()->index; + printk(BIOS_INFO, "Initializing Topology Extensions Support for CPU %u\n", cpu_idx); + } + /* DisableCf8ExtCfg */ msr = rdmsr(NB_CFG_MSR); msr.hi &= ~(1 << (46 - 32));