[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add GPIOs for Alder Lake SOC

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )

Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC
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Patch Set 5:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... 
File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:

https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... 
PS2, Line 309:
> HI Angel, Before opening those code, i have confirmed from EDS owner that those GPIOs are not intend […]

Proving little more information here all GPIO PIN that Michael has asked like Azalia, CPU, VGPIO are part of GPIO COMM 3 which we don't expose for Linux driver and BIOS. i hope this is good to have information.