[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Add GPIOs for Alder Lake SOC

[Michael Niewöhner (Code Review)]

Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )

Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... 
File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:

https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... 
PS2, Line 309:
> these are not part of SoC EDS chapter as i have added above, hence don't expect BIOS to configure.

FSP configures some of them (there are even UPDs which do nothing but set a pin to NF1...). Isn't FSP part of "BIOS"?

Curious, are they documented elsewhere except FSP source?