Tristan Hsieh has uploaded this change for review. ( https://review.coreboot.org/29193
Change subject: mediatek/mt8183: add pmic and pwrap support ......................................................................
mediatek/mt8183: add pmic and pwrap support
BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui
Change-Id: Ie16c2ba83dae1849aa39185c9577c2a9a2e33fa3 Signed-off-by: Hsin-Hsiung Wang hsin-hsiung.wang@mediatek.com --- M src/soc/mediatek/mt8183/Makefile.inc M src/soc/mediatek/mt8183/include/soc/addressmap.h A src/soc/mediatek/mt8183/include/soc/mt6358.h A src/soc/mediatek/mt8183/include/soc/pmic_wrap.h A src/soc/mediatek/mt8183/mt6358.c A src/soc/mediatek/mt8183/pmic_wrap.c M src/soc/mediatek/mt8183/soc.c 7 files changed, 1,477 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/29193/1
diff --git a/src/soc/mediatek/mt8183/Makefile.inc b/src/soc/mediatek/mt8183/Makefile.inc index 4a5490b..2b370cd 100644 --- a/src/soc/mediatek/mt8183/Makefile.inc +++ b/src/soc/mediatek/mt8183/Makefile.inc @@ -39,6 +39,8 @@ ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c ramstage-y += ../common/usb.c ramstage-y += ../common/wdt.c +ramstage-y += mt6358.c +ramstage-y += pmic_wrap.c
CPPFLAGS_common += -Isrc/soc/mediatek/mt8183/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include diff --git a/src/soc/mediatek/mt8183/include/soc/addressmap.h b/src/soc/mediatek/mt8183/include/soc/addressmap.h index 1ba9cc8..b11d126 100644 --- a/src/soc/mediatek/mt8183/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8183/include/soc/addressmap.h @@ -26,9 +26,10 @@ INFRACFG_AO_BASE = IO_PHYS + 0x00001000, GPIO_BASE = IO_PHYS + 0x00005000, SPM_BASE = IO_PHYS + 0x00006000, - RGU_BASE = IO_PHYS + 0x00007000, + RGU_BASE = IO_PHYS + 0x00007000, GPT_BASE = IO_PHYS + 0x00008000, APMIXED_BASE = IO_PHYS + 0x0000C000, + PWRAP_BASE = IO_PHYS + 0x0000D000, EMI_BASE = IO_PHYS + 0x00219000, EMI_MPU_BASE = IO_PHYS + 0x00226000, DRAMC_CH_BASE = IO_PHYS + 0x00228000, diff --git a/src/soc/mediatek/mt8183/include/soc/mt6358.h b/src/soc/mediatek/mt8183/include/soc/mt6358.h new file mode 100644 index 0000000..137b62c --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/mt6358.h @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MT6358_H__ +#define __SOC_MEDIATEK_MT6358_H__ + +enum { + PMIC_SWCID = 0x000A, + PMIC_TOP_RST_MISC = 0x014C, + PMIC_TOP_RST_MISC_SET = 0x014E, + PMIC_TOP_RST_MISC_CLR = 0x0150, + PMIC_SMPS_ANA_CON0 = 0x1808, + PMIC_TOP_TMA_KEY = 0x03A8, + PMIC_CPSDSA4 = 0x0A2E, +}; + +void mt6358_init(void); +u32 pmic_read_interface(u32 reg, u32 mask, u32 shift); +void pmic_config_interface(u32 reg, u32 val, u32 mask, u32 shift); +#endif /* __SOC_MEDIATEK_MT6358_H__ */ diff --git a/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h new file mode 100644 index 0000000..4dd7628 --- /dev/null +++ b/src/soc/mediatek/mt8183/include/soc/pmic_wrap.h @@ -0,0 +1,672 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __SOC_MEDIATEK_MT8183_PMIC_WRAP_H__ +#define __SOC_MEDIATEK_MT8183_PMIC_WRAP_H__ + +#include <soc/addressmap.h> +#include <types.h> + +#define WRAP_RD32(addr) (*(volatile unsigned int *)(addr)) +#define WRAP_WR32(addr,data) ((*(volatile unsigned int *)(addr)) = (unsigned int)data) + +s32 pwrap_read(u32 adr, u32 *rdata); +s32 pwrap_write(u32 adr, u32 wdata); +s32 pwrap_init(void); + +struct mt8183_pwrap_regs { + u32 mux_sel; + u32 wrap_en; + u32 dio_en; + u32 si_sample_ctrl; + u32 si_sample_ctrl_ulposc; + u32 rddmy; + u32 cshext_write; + u32 cshext_read; + u32 cslext_write; + u32 cslext_read; + u32 ext_ck_write; + u32 ext_ck_read; + u32 staupd_ctrl; + u32 staupd_grpen; + u32 eint_sta0_adr; + u32 eint_sta1_adr; + u32 eint_sta; + u32 eint_clr; + u32 eint_ctrl; + u32 staupd_man_trig; + u32 staupd_sta; + u32 wrap_sta; + u32 harb_init; + u32 harb_hprio; + u32 hprio_arb_en; + u32 harb_sta0; + u32 harb_sta1; + u32 harb_sta2; + u32 man_en; + u32 man_cmd; + u32 man_rdata; + u32 man_vldclr; + u32 wacs0_en; + u32 init_done0; + u32 wacs1_en; + u32 init_done1; + u32 wacs2_en; + u32 init_done2; + u32 wacs3_en; + u32 init_done3; + u32 wacs_p2p_en; + u32 init_done_p2p; + u32 wacs_md32_en; + u32 init_done_md32; + u32 int0_en; + u32 int0_flg_raw; + u32 int0_flg; + u32 int0_clr; + u32 int1_en; + u32 int1_flg_raw; + u32 int1_flg; + u32 int1_clr; + u32 sig_adr; + u32 sig_mode; + u32 sig_value; + u32 sig_errval; + u32 crc_en; + u32 timer_en; + u32 timer_sta; + u32 wdt_unit; + u32 wdt_src_en_0; + u32 wdt_src_en_1; + u32 wdt_flg_0; + u32 wdt_flg_1; + u32 debug_int_sel; + u32 dvfs_adr0; + u32 dvfs_wdata0; + u32 dvfs_adr1; + u32 dvfs_wdata1; + u32 dvfs_adr2; + u32 dvfs_wdata2; + u32 dvfs_adr3; + u32 dvfs_wdata3; + u32 dvfs_adr4; + u32 dvfs_wdata4; + u32 dvfs_adr5; + u32 dvfs_wdata5; + u32 dvfs_adr6; + u32 dvfs_wdata6; + u32 dvfs_adr7; + u32 dvfs_wdata7; + u32 dvfs_adr8; + u32 dvfs_wdata8; + u32 dvfs_adr9; + u32 dvfs_wdata9; + u32 dvfs_adr10; + u32 dvfs_wdata10; + u32 dvfs_adr11; + u32 dvfs_wdata11; + u32 dvfs_adr12; + u32 dvfs_wdata12; + u32 dvfs_adr13; + u32 dvfs_wdata13; + u32 dvfs_adr14; + u32 dvfs_wdata14; + u32 dvfs_adr15; + u32 dvfs_wdata15; + u32 dcxo_enable; + u32 dcxo_conn_adr0; + u32 dcxo_conn_wdata0; + u32 dcxo_conn_adr1; + u32 dcxo_conn_wdata1; + u32 dcxo_nfc_adr0; + u32 dcxo_nfc_wdata0; + u32 dcxo_nfc_adr1; + u32 dcxo_nfc_wdata1; + u32 spminf_sta_0; + u32 spminf_sta_1; + u32 spminf_backup_sta; + u32 scpinf_sta; + u32 cipher_key_sel; + u32 cipher_iv_sel; + u32 cipher_en; + u32 cipher_rdy; + u32 cipher_mode; + u32 cipher_swrst; + u32 dcm_en; + u32 dcm_spi_dbc_prd; + u32 dcm_dbc_prd; + u32 int_gps_auxadc_cmd_addr; + u32 int_gps_auxadc_cmd; + u32 int_gps_auxadc_rdata_addr; + u32 ext_gps_auxadc_rdata_addr; + u32 gpsinf_0_sta; + u32 gpsinf_1_sta; + u32 md_adcinf_ctrl; + u32 md_auxadc_rdata_latest_addr; + u32 md_auxadc_rdata_wp_addr; + u32 md_auxadc_rdata_0_addr; + u32 md_auxadc_rdata_1_addr; + u32 md_auxadc_rdata_2_addr; + u32 md_auxadc_rdata_3_addr; + u32 md_auxadc_rdata_4_addr; + u32 md_auxadc_rdata_5_addr; + u32 md_auxadc_rdata_6_addr; + u32 md_auxadc_rdata_7_addr; + u32 md_auxadc_rdata_8_addr; + u32 md_auxadc_rdata_9_addr; + u32 md_auxadc_rdata_10_addr; + u32 md_auxadc_rdata_11_addr; + u32 md_auxadc_rdata_12_addr; + u32 md_auxadc_rdata_13_addr; + u32 md_auxadc_rdata_14_addr; + u32 md_auxadc_rdata_15_addr; + u32 md_auxadc_rdata_16_addr; + u32 md_auxadc_rdata_17_addr; + u32 md_auxadc_rdata_18_addr; + u32 md_auxadc_rdata_19_addr; + u32 md_auxadc_rdata_20_addr; + u32 md_auxadc_rdata_21_addr; + u32 md_auxadc_rdata_22_addr; + u32 md_auxadc_rdata_23_addr; + u32 md_auxadc_rdata_24_addr; + u32 md_auxadc_rdata_25_addr; + u32 md_auxadc_rdata_26_addr; + u32 md_auxadc_rdata_27_addr; + u32 md_auxadc_rdata_28_addr; + u32 md_auxadc_rdata_29_addr; + u32 md_auxadc_rdata_30_addr; + u32 md_auxadc_rdata_31_addr; + u32 md_adcinf_0_sta_0; + u32 md_adcinf_0_sta_1; + u32 md_adcinf_1_sta_0; + u32 md_adcinf_1_sta_1; + u32 swrst; + u32 spm_sleep_gating_ctrl; + u32 scp_sleep_gating_ctrl; + u32 priority_user_sel_0; + u32 priority_user_sel_1; + u32 priority_user_sel_2; + u32 priority_user_sel_3; + u32 priority_user_sel_4; + u32 arbiter_out_sel_0; + u32 arbiter_out_sel_1; + u32 arbiter_out_sel_2; + u32 arbiter_out_sel_3; + u32 arbiter_out_sel_4; + u32 starv_counter_0; + u32 starv_counter_1; + u32 starv_counter_2; + u32 starv_counter_3; + u32 starv_counter_4; + u32 starv_counter_5; + u32 starv_counter_6; + u32 starv_counter_7; + u32 starv_counter_8; + u32 starv_counter_9; + u32 starv_counter_10; + u32 starv_counter_11; + u32 starv_counter_12; + u32 starv_counter_13; + u32 starv_counter_14; + u32 starv_counter_15; + u32 starv_counter_16; + u32 starv_counter_0_status; + u32 starv_counter_1_status; + u32 starv_counter_2_status; + u32 starv_counter_3_status; + u32 starv_counter_4_status; + u32 starv_counter_5_status; + u32 starv_counter_6_status; + u32 starv_counter_7_status; + u32 starv_counter_8_status; + u32 starv_counter_9_status; + u32 starv_counter_10_status; + u32 starv_counter_11_status; + u32 starv_counter_12_status; + u32 starv_counter_13_status; + u32 starv_counter_14_status; + u32 starv_counter_15_status; + u32 starv_counter_16_status; + u32 starv_counter_clr; + u32 starv_prio_status; + u32 monitor_ctrl_0; + u32 monitor_ctrl_1; + u32 monitor_ctrl_2; + u32 monitor_ctrl_3; + u32 channel_sequence_0; + u32 channel_sequence_1; + u32 channel_sequence_2; + u32 channel_sequence_3; + u32 cmd_sequence_0; + u32 cmd_sequence_1; + u32 cmd_sequence_2; + u32 cmd_sequence_3; + u32 cmd_sequence_4; + u32 cmd_sequence_5; + u32 cmd_sequence_6; + u32 cmd_sequence_7; + u32 wdata_sequence_0; + u32 wdata_sequence_1; + u32 wdata_sequence_2; + u32 wdata_sequence_3; + u32 wdata_sequence_4; + u32 wdata_sequence_5; + u32 wdata_sequence_6; + u32 wdata_sequence_7; + u32 debug_sw_driver_0; + u32 debug_sw_driver_1; + u32 debug_sw_driver_2; + u32 debug_sw_driver_3; + u32 debug_sw_driver_4; + u32 debug_sw_driver_5; + u32 bwc_options; + u32 reserved1[524]; + u32 wacs0_cmd; + u32 wacs0_rdata; + u32 wacs0_vldclr; + u32 reserved2; + u32 wacs1_cmd; + u32 wacs1_rdata; + u32 wacs1_vldclr; + u32 reserved3; + u32 wacs2_cmd; + u32 wacs2_rdata; + u32 wacs2_vldclr; + u32 reserved4; + u32 wacs3_cmd; + u32 wacs3_rdata; + u32 wacs3_vldclr; +}; + +check_member(mt8183_pwrap_regs, mux_sel, 0x0); +check_member(mt8183_pwrap_regs, wrap_en, 0x4); +check_member(mt8183_pwrap_regs, dio_en, 0x8); +check_member(mt8183_pwrap_regs, si_sample_ctrl, 0xC); +check_member(mt8183_pwrap_regs, si_sample_ctrl_ulposc, 0x10); +check_member(mt8183_pwrap_regs, rddmy, 0x14); +check_member(mt8183_pwrap_regs, cshext_write, 0x18); +check_member(mt8183_pwrap_regs, cshext_read, 0x1C); +check_member(mt8183_pwrap_regs, cslext_write, 0x20); +check_member(mt8183_pwrap_regs, cslext_read, 0x24); +check_member(mt8183_pwrap_regs, ext_ck_write, 0x28); +check_member(mt8183_pwrap_regs, ext_ck_read, 0x2C); +check_member(mt8183_pwrap_regs, staupd_ctrl, 0x30); +check_member(mt8183_pwrap_regs, staupd_grpen, 0x34); +check_member(mt8183_pwrap_regs, eint_sta0_adr, 0x38); +check_member(mt8183_pwrap_regs, eint_sta1_adr, 0x3C); +check_member(mt8183_pwrap_regs, eint_sta, 0x40); +check_member(mt8183_pwrap_regs, eint_clr, 0x44); +check_member(mt8183_pwrap_regs, eint_ctrl, 0x48); +check_member(mt8183_pwrap_regs, staupd_man_trig, 0x4C); +check_member(mt8183_pwrap_regs, staupd_sta, 0x50); +check_member(mt8183_pwrap_regs, wrap_sta, 0x54); +check_member(mt8183_pwrap_regs, harb_init, 0x58); +check_member(mt8183_pwrap_regs, harb_hprio, 0x5C); +check_member(mt8183_pwrap_regs, hprio_arb_en, 0x60); +check_member(mt8183_pwrap_regs, harb_sta0, 0x64); +check_member(mt8183_pwrap_regs, harb_sta1, 0x68); +check_member(mt8183_pwrap_regs, harb_sta2, 0x6C); +check_member(mt8183_pwrap_regs, man_en, 0x70); +check_member(mt8183_pwrap_regs, man_cmd, 0x74); +check_member(mt8183_pwrap_regs, man_rdata, 0x78); +check_member(mt8183_pwrap_regs, man_vldclr, 0x7C); +check_member(mt8183_pwrap_regs, wacs0_en, 0x80); +check_member(mt8183_pwrap_regs, init_done0, 0x84); +check_member(mt8183_pwrap_regs, wacs1_en, 0x88); +check_member(mt8183_pwrap_regs, init_done1, 0x8C); +check_member(mt8183_pwrap_regs, wacs2_en, 0x90); +check_member(mt8183_pwrap_regs, init_done2, 0x94); +check_member(mt8183_pwrap_regs, wacs3_en, 0x98); +check_member(mt8183_pwrap_regs, init_done3, 0x9C); +check_member(mt8183_pwrap_regs, wacs_p2p_en, 0xA0); +check_member(mt8183_pwrap_regs, init_done_p2p, 0xA4); +check_member(mt8183_pwrap_regs, wacs_md32_en, 0xA8); +check_member(mt8183_pwrap_regs, init_done_md32, 0xAC); +check_member(mt8183_pwrap_regs, int0_en, 0xB0); +check_member(mt8183_pwrap_regs, int0_flg_raw, 0xB4); +check_member(mt8183_pwrap_regs, int0_flg, 0xB8); +check_member(mt8183_pwrap_regs, int0_clr, 0xBC); +check_member(mt8183_pwrap_regs, int1_en, 0xC0); +check_member(mt8183_pwrap_regs, int1_flg_raw, 0xC4); +check_member(mt8183_pwrap_regs, int1_flg, 0xC8); +check_member(mt8183_pwrap_regs, int1_clr, 0xCC); +check_member(mt8183_pwrap_regs, sig_adr, 0xD0); +check_member(mt8183_pwrap_regs, sig_mode, 0xD4); +check_member(mt8183_pwrap_regs, sig_value, 0xD8); +check_member(mt8183_pwrap_regs, sig_errval, 0xDC); +check_member(mt8183_pwrap_regs, crc_en, 0xE0); +check_member(mt8183_pwrap_regs, timer_en, 0xE4); +check_member(mt8183_pwrap_regs, timer_sta, 0xE8); +check_member(mt8183_pwrap_regs, wdt_unit, 0xEC); +check_member(mt8183_pwrap_regs, wdt_src_en_0, 0xF0); +check_member(mt8183_pwrap_regs, wdt_src_en_1, 0xF4); +check_member(mt8183_pwrap_regs, wdt_flg_0, 0xF8); +check_member(mt8183_pwrap_regs, wdt_flg_1, 0xFC); +check_member(mt8183_pwrap_regs, debug_int_sel, 0x100); +check_member(mt8183_pwrap_regs, dvfs_adr0, 0x104); +check_member(mt8183_pwrap_regs, dvfs_wdata0, 0x108); +check_member(mt8183_pwrap_regs, dvfs_adr1, 0x10C); +check_member(mt8183_pwrap_regs, dvfs_wdata1, 0x110); +check_member(mt8183_pwrap_regs, dvfs_adr2, 0x114); +check_member(mt8183_pwrap_regs, dvfs_wdata2, 0x118); +check_member(mt8183_pwrap_regs, dvfs_adr3, 0x11C); +check_member(mt8183_pwrap_regs, dvfs_wdata3, 0x120); +check_member(mt8183_pwrap_regs, dvfs_adr4, 0x124); +check_member(mt8183_pwrap_regs, dvfs_wdata4, 0x128); +check_member(mt8183_pwrap_regs, dvfs_adr5, 0x12C); +check_member(mt8183_pwrap_regs, dvfs_wdata5, 0x130); +check_member(mt8183_pwrap_regs, dvfs_adr6, 0x134); +check_member(mt8183_pwrap_regs, dvfs_wdata6, 0x138); +check_member(mt8183_pwrap_regs, dvfs_adr7, 0x13C); +check_member(mt8183_pwrap_regs, dvfs_wdata7, 0x140); +check_member(mt8183_pwrap_regs, dvfs_adr8, 0x144); +check_member(mt8183_pwrap_regs, dvfs_wdata8, 0x148); +check_member(mt8183_pwrap_regs, dvfs_adr9, 0x14C); +check_member(mt8183_pwrap_regs, dvfs_wdata9, 0x150); +check_member(mt8183_pwrap_regs, dvfs_adr10, 0x154); +check_member(mt8183_pwrap_regs, dvfs_wdata10, 0x158); +check_member(mt8183_pwrap_regs, dvfs_adr11, 0x15C); +check_member(mt8183_pwrap_regs, dvfs_wdata11, 0x160); +check_member(mt8183_pwrap_regs, dvfs_adr12, 0x164); +check_member(mt8183_pwrap_regs, dvfs_wdata12, 0x168); +check_member(mt8183_pwrap_regs, dvfs_adr13, 0x16C); +check_member(mt8183_pwrap_regs, dvfs_wdata13, 0x170); +check_member(mt8183_pwrap_regs, dvfs_adr14, 0x174); +check_member(mt8183_pwrap_regs, dvfs_wdata14, 0x178); +check_member(mt8183_pwrap_regs, dvfs_adr15, 0x17C); +check_member(mt8183_pwrap_regs, dvfs_wdata15, 0x180); +check_member(mt8183_pwrap_regs, dcxo_enable, 0x184); +check_member(mt8183_pwrap_regs, dcxo_conn_adr0, 0x188); +check_member(mt8183_pwrap_regs, dcxo_conn_wdata0, 0x18C); +check_member(mt8183_pwrap_regs, dcxo_conn_adr1, 0x190); +check_member(mt8183_pwrap_regs, dcxo_conn_wdata1, 0x194); +check_member(mt8183_pwrap_regs, dcxo_nfc_adr0, 0x198); +check_member(mt8183_pwrap_regs, dcxo_nfc_wdata0, 0x19C); +check_member(mt8183_pwrap_regs, dcxo_nfc_adr1, 0x1A0); +check_member(mt8183_pwrap_regs, dcxo_nfc_wdata1, 0x1A4); +check_member(mt8183_pwrap_regs, spminf_sta_0, 0x1A8); +check_member(mt8183_pwrap_regs, spminf_sta_1, 0x1AC); +check_member(mt8183_pwrap_regs, spminf_backup_sta, 0x1B0); +check_member(mt8183_pwrap_regs, scpinf_sta, 0x1B4); +check_member(mt8183_pwrap_regs, cipher_key_sel, 0x1B8); +check_member(mt8183_pwrap_regs, cipher_iv_sel, 0x1BC); +check_member(mt8183_pwrap_regs, cipher_en, 0x1C0); +check_member(mt8183_pwrap_regs, cipher_rdy, 0x1C4); +check_member(mt8183_pwrap_regs, cipher_mode, 0x1C8); +check_member(mt8183_pwrap_regs, cipher_swrst, 0x1CC); +check_member(mt8183_pwrap_regs, dcm_en, 0x1D0); +check_member(mt8183_pwrap_regs, dcm_spi_dbc_prd, 0x1D4); +check_member(mt8183_pwrap_regs, dcm_dbc_prd, 0x1D8); +check_member(mt8183_pwrap_regs, int_gps_auxadc_cmd_addr, 0x1DC); +check_member(mt8183_pwrap_regs, int_gps_auxadc_cmd, 0x1E0); +check_member(mt8183_pwrap_regs, int_gps_auxadc_rdata_addr, 0x1E4); +check_member(mt8183_pwrap_regs, ext_gps_auxadc_rdata_addr, 0x1E8); +check_member(mt8183_pwrap_regs, gpsinf_0_sta, 0x1EC); +check_member(mt8183_pwrap_regs, gpsinf_1_sta, 0x1F0); +check_member(mt8183_pwrap_regs, md_adcinf_ctrl, 0x1F4); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_latest_addr, 0x1F8); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_wp_addr, 0x1FC); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_0_addr, 0x200); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_1_addr, 0x204); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_2_addr, 0x208); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_3_addr, 0x20C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_4_addr, 0x210); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_5_addr, 0x214); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_6_addr, 0x218); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_7_addr, 0x21C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_8_addr, 0x220); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_9_addr, 0x224); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_10_addr, 0x228); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_11_addr, 0x22C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_12_addr, 0x230); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_13_addr, 0x234); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_14_addr, 0x238); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_15_addr, 0x23C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_16_addr, 0x240); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_17_addr, 0x244); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_18_addr, 0x248); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_19_addr, 0x24C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_20_addr, 0x250); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_21_addr, 0x254); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_22_addr, 0x258); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_23_addr, 0x25C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_24_addr, 0x260); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_25_addr, 0x264); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_26_addr, 0x268); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_27_addr, 0x26C); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_28_addr, 0x270); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_29_addr, 0x274); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_30_addr, 0x278); +check_member(mt8183_pwrap_regs, md_auxadc_rdata_31_addr, 0x27C); +check_member(mt8183_pwrap_regs, md_adcinf_0_sta_0, 0x280); +check_member(mt8183_pwrap_regs, md_adcinf_0_sta_1, 0x284); +check_member(mt8183_pwrap_regs, md_adcinf_1_sta_0, 0x288); +check_member(mt8183_pwrap_regs, md_adcinf_1_sta_1, 0x28C); +check_member(mt8183_pwrap_regs, swrst, 0x290); +check_member(mt8183_pwrap_regs, spm_sleep_gating_ctrl, 0x294); +check_member(mt8183_pwrap_regs, scp_sleep_gating_ctrl, 0x298); +check_member(mt8183_pwrap_regs, priority_user_sel_0, 0x29C); +check_member(mt8183_pwrap_regs, priority_user_sel_1, 0x2A0); +check_member(mt8183_pwrap_regs, priority_user_sel_2, 0x2A4); +check_member(mt8183_pwrap_regs, priority_user_sel_3, 0x2A8); +check_member(mt8183_pwrap_regs, priority_user_sel_4, 0x2AC); +check_member(mt8183_pwrap_regs, arbiter_out_sel_0, 0x2B0); +check_member(mt8183_pwrap_regs, arbiter_out_sel_1, 0x2B4); +check_member(mt8183_pwrap_regs, arbiter_out_sel_2, 0x2B8); +check_member(mt8183_pwrap_regs, arbiter_out_sel_3, 0x2BC); +check_member(mt8183_pwrap_regs, arbiter_out_sel_4, 0x2C0); +check_member(mt8183_pwrap_regs, starv_counter_0, 0x2C4); +check_member(mt8183_pwrap_regs, starv_counter_1, 0x2C8); +check_member(mt8183_pwrap_regs, starv_counter_2, 0x2CC); +check_member(mt8183_pwrap_regs, starv_counter_3, 0x2D0); +check_member(mt8183_pwrap_regs, starv_counter_4, 0x2D4); +check_member(mt8183_pwrap_regs, starv_counter_5, 0x2D8); +check_member(mt8183_pwrap_regs, starv_counter_6, 0x2DC); +check_member(mt8183_pwrap_regs, starv_counter_7, 0x2E0); +check_member(mt8183_pwrap_regs, starv_counter_8, 0x2E4); +check_member(mt8183_pwrap_regs, starv_counter_9, 0x2E8); +check_member(mt8183_pwrap_regs, starv_counter_10, 0x2EC); +check_member(mt8183_pwrap_regs, starv_counter_11, 0x2F0); +check_member(mt8183_pwrap_regs, starv_counter_12, 0x2F4); +check_member(mt8183_pwrap_regs, starv_counter_13, 0x2F8); +check_member(mt8183_pwrap_regs, starv_counter_14, 0x2FC); +check_member(mt8183_pwrap_regs, starv_counter_15, 0x300); +check_member(mt8183_pwrap_regs, starv_counter_16, 0x304); +check_member(mt8183_pwrap_regs, starv_counter_0_status, 0x308); +check_member(mt8183_pwrap_regs, starv_counter_1_status, 0x30C); +check_member(mt8183_pwrap_regs, starv_counter_2_status, 0x310); +check_member(mt8183_pwrap_regs, starv_counter_3_status, 0x314); +check_member(mt8183_pwrap_regs, starv_counter_4_status, 0x318); +check_member(mt8183_pwrap_regs, starv_counter_5_status, 0x31C); +check_member(mt8183_pwrap_regs, starv_counter_6_status, 0x320); +check_member(mt8183_pwrap_regs, starv_counter_7_status, 0x324); +check_member(mt8183_pwrap_regs, starv_counter_8_status, 0x328); +check_member(mt8183_pwrap_regs, starv_counter_9_status, 0x32C); +check_member(mt8183_pwrap_regs, starv_counter_10_status, 0x330); +check_member(mt8183_pwrap_regs, starv_counter_11_status, 0x334); +check_member(mt8183_pwrap_regs, starv_counter_12_status, 0x338); +check_member(mt8183_pwrap_regs, starv_counter_13_status, 0x33C); +check_member(mt8183_pwrap_regs, starv_counter_14_status, 0x340); +check_member(mt8183_pwrap_regs, starv_counter_15_status, 0x344); +check_member(mt8183_pwrap_regs, starv_counter_16_status, 0x348); +check_member(mt8183_pwrap_regs, starv_counter_clr, 0x34C); +check_member(mt8183_pwrap_regs, starv_prio_status, 0x350); +check_member(mt8183_pwrap_regs, monitor_ctrl_0, 0x354); +check_member(mt8183_pwrap_regs, monitor_ctrl_1, 0x358); +check_member(mt8183_pwrap_regs, monitor_ctrl_2, 0x35C); +check_member(mt8183_pwrap_regs, monitor_ctrl_3, 0x360); +check_member(mt8183_pwrap_regs, channel_sequence_0, 0x364); +check_member(mt8183_pwrap_regs, channel_sequence_1, 0x368); +check_member(mt8183_pwrap_regs, channel_sequence_2, 0x36C); +check_member(mt8183_pwrap_regs, channel_sequence_3, 0x370); +check_member(mt8183_pwrap_regs, cmd_sequence_0, 0x374); +check_member(mt8183_pwrap_regs, cmd_sequence_1, 0x378); +check_member(mt8183_pwrap_regs, cmd_sequence_2, 0x37C); +check_member(mt8183_pwrap_regs, cmd_sequence_3, 0x380); +check_member(mt8183_pwrap_regs, cmd_sequence_4, 0x384); +check_member(mt8183_pwrap_regs, cmd_sequence_5, 0x388); +check_member(mt8183_pwrap_regs, cmd_sequence_6, 0x38C); +check_member(mt8183_pwrap_regs, cmd_sequence_7, 0x390); +check_member(mt8183_pwrap_regs, wdata_sequence_0, 0x394); +check_member(mt8183_pwrap_regs, wdata_sequence_1, 0x398); +check_member(mt8183_pwrap_regs, wdata_sequence_2, 0x39C); +check_member(mt8183_pwrap_regs, wdata_sequence_3, 0x3A0); +check_member(mt8183_pwrap_regs, wdata_sequence_4, 0x3A4); +check_member(mt8183_pwrap_regs, wdata_sequence_5, 0x3A8); +check_member(mt8183_pwrap_regs, wdata_sequence_6, 0x3AC); +check_member(mt8183_pwrap_regs, wdata_sequence_7, 0x3B0); +check_member(mt8183_pwrap_regs, debug_sw_driver_0, 0x3B4); +check_member(mt8183_pwrap_regs, debug_sw_driver_1, 0x3B8); +check_member(mt8183_pwrap_regs, debug_sw_driver_2, 0x3BC); +check_member(mt8183_pwrap_regs, debug_sw_driver_3, 0x3C0); +check_member(mt8183_pwrap_regs, debug_sw_driver_4, 0x3C4); +check_member(mt8183_pwrap_regs, debug_sw_driver_5, 0x3C8); +check_member(mt8183_pwrap_regs, bwc_options, 0x3CC); +check_member(mt8183_pwrap_regs, reserved1, 0x3D0); +check_member(mt8183_pwrap_regs, wacs0_cmd, 0xC00); +check_member(mt8183_pwrap_regs, wacs0_rdata, 0xC04); +check_member(mt8183_pwrap_regs, wacs0_vldclr, 0xC08); +check_member(mt8183_pwrap_regs, reserved2, 0xC0C); +check_member(mt8183_pwrap_regs, wacs1_cmd, 0xC10); +check_member(mt8183_pwrap_regs, wacs1_rdata, 0xC14); +check_member(mt8183_pwrap_regs, wacs1_vldclr, 0xC18); +check_member(mt8183_pwrap_regs, reserved3, 0xC1C); +check_member(mt8183_pwrap_regs, wacs2_cmd, 0xC20); +check_member(mt8183_pwrap_regs, wacs2_rdata, 0xC24); +check_member(mt8183_pwrap_regs, wacs2_vldclr, 0xC28); +check_member(mt8183_pwrap_regs, reserved4, 0xC2C); +check_member(mt8183_pwrap_regs, wacs3_cmd, 0xC30); +check_member(mt8183_pwrap_regs, wacs3_rdata, 0xC34); +check_member(mt8183_pwrap_regs, wacs3_vldclr, 0xC38); + +static struct mt8183_pwrap_regs * const mt8183_pwrap = (void *)PWRAP_BASE; + +/* timeout setting */ +enum { + TIMEOUT_READ_US = 255, + TIMEOUT_WAIT_IDLE_US = 255 +}; + +enum { + WACS2 = 1 << 2 +}; + +/* PMIC registers */ +enum { + PMIC_BASE = 0x0000, + PMIC_SMT_CON1 = PMIC_BASE + 0x0030, + PMIC_DRV_CON1 = PMIC_BASE + 0x0038, + PMIC_FILTER_CON0 = PMIC_BASE + 0x0040, + PMIC_GPIO_PULLEN0_CLR = PMIC_BASE + 0x0098, + PMIC_RG_SPI_CON0 = PMIC_BASE + 0x0408, + PMIC_RG_SPI_RECORD0 = PMIC_BASE + 0x040A, + PMIC_DEW_DIO_EN = PMIC_BASE + 0x040C, + PMIC_DEW_READ_TEST = PMIC_BASE + 0x040E, + PMIC_DEW_WRITE_TEST = PMIC_BASE + 0x0410, + PMIC_DEW_CRC_EN = PMIC_BASE + 0x0414, + PMIC_DEW_CRC_VAL = PMIC_BASE + 0x0416, + PMIC_DEW_RDDMY_NO = PMIC_BASE + 0x0426, + PMIC_CPU_INT_STA = PMIC_BASE + 0x042E, + PMIC_RG_SPI_CON2 = PMIC_BASE + 0x0432, + PMIC_RG_SPI_CON3 = PMIC_BASE + 0x0434, + PMIC_RG_SPI_CON4 = PMIC_BASE + 0x0436, + PMIC_RG_SPI_CON5 = PMIC_BASE + 0x0438, + PMIC_RG_SPI_CON6 = PMIC_BASE + 0x043A, + PMIC_RG_SPI_CON7 = PMIC_BASE + 0x043C, + PMIC_RG_SPI_CON8 = PMIC_BASE + 0x043E, + PMIC_RG_SPI_CON13 = PMIC_BASE + 0x0448, + PMIC_SPISLV_KEY = PMIC_BASE + 0x044A, + PMIC_PPCCTL0 = PMIC_BASE + 0x0A08, + PMIC_AUXADC_ADC17 = PMIC_BASE + 0x10AA, + PMIC_AUXADC_ADC31 = PMIC_BASE + 0x10C6, + PMIC_AUXADC_ADC32 = PMIC_BASE + 0x10C8, + PMIC_AUXADC_ADC35 = PMIC_BASE + 0x10CE, + PMIC_AUXADC_RQST0 = PMIC_BASE + 0x1108, + PMIC_AUXADC_RQST1 = PMIC_BASE + 0x110A, +}; + +enum { + RDATA_WACS_RDATA_SHIFT = 0, + RDATA_WACS_FSM_SHIFT = 16, + RDATA_SYNC_IDLE_SHIFT = 20, + RDATA_INIT_DONE_SHIFT, +}; + +enum { + RDATA_WACS_RDATA_MASK = 0xffff, + RDATA_WACS_FSM_MASK = 0x7, + RDATA_SYNC_IDLE_MASK = 0x1, + RDATA_INIT_DONE_MASK = 0x1, +}; + +/* WACS_FSM */ +enum { + WACS_FSM_IDLE = 0x00, + WACS_FSM_REQ = 0x02, + WACS_FSM_WFDLE = 0x04, /* wait for dle, wait for read data done */ + WACS_FSM_WFVLDCLR = 0x06, /* finish read data, wait for valid flag + * clearing */ + WACS_SYNC_IDLE = 0x01, + WACS_INIT_DONE = 0x01, +}; + +enum { + DEFAULT_VALUE_READ_TEST = 0x5aa5, + WRITE_TEST_VALUE = 0xa55a +}; + +enum pmic_regck { + REG_CLOCK_18MHZ = 1, + REG_CLOCK_SAFE_MODE +}; + +/* manual commnd */ +enum { + OP_WR = 0x1, + OP_CSH = 0x0, + OP_CSL = 0x1, + OP_OUTS = 0x8, +}; + +/* error information flag */ +enum { + E_PWR_INVALID_ARG = 1, + E_PWR_INVALID_RW = 2, + E_PWR_INVALID_ADDR = 3, + E_PWR_INVALID_WDAT = 4, + E_PWR_INVALID_OP_MANUAL = 5, + E_PWR_NOT_IDLE_STATE = 6, + E_PWR_NOT_INIT_DONE = 7, + E_PWR_NOT_INIT_DONE_READ = 8, + E_PWR_WAIT_IDLE_TIMEOUT = 9, + E_PWR_WAIT_IDLE_TIMEOUT_READ = 10, + E_PWR_INIT_SIDLY_FAIL = 11, + E_PWR_RESET_TIMEOUT = 12, + E_PWR_TIMEOUT = 13, + E_PWR_INIT_RESET_SPI = 20, + E_PWR_INIT_SIDLY = 21, + E_PWR_INIT_REG_CLOCK = 22, + E_PWR_INIT_ENABLE_PMIC = 23, + E_PWR_INIT_DIO = 24, + E_PWR_INIT_CIPHER = 25, + E_PWR_INIT_WRITE_TEST = 26, + E_PWR_INIT_ENABLE_CRC = 27, + E_PWR_INIT_ENABLE_DEWRAP = 28, + E_PWR_INIT_ENABLE_EVENT = 29, + E_PWR_READ_TEST_FAIL = 30, + E_PWR_WRITE_TEST_FAIL = 31, + E_PWR_SWITCH_DIO = 32 +}; + +#endif /* __SOC_MEDIATEK_MT8183_PMIC_WRAP_H__ */ \ No newline at end of file diff --git a/src/soc/mediatek/mt8183/mt6358.c b/src/soc/mediatek/mt8183/mt6358.c new file mode 100644 index 0000000..d8c2adb --- /dev/null +++ b/src/soc/mediatek/mt8183/mt6358.c @@ -0,0 +1,76 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <assert.h> +#include <console/console.h> +#include <soc/pmic_wrap.h> +#include <soc/mt6358.h> + +#if 1 +#define DEBUG_PMIC(x...) printk(BIOS_INFO, x) +#else +#define DEBUG_PMIC(x...) +#endif + +u32 pmic_read_interface(u32 reg, u32 mask, u32 shift) +{ + u32 rdata; + + pwrap_read(reg, &rdata); + rdata &= (mask << shift); + rdata = (rdata >> shift); + + DEBUG_PMIC("[%s] Reg[%#x]=%#x\n", + __func__, reg, rdata); + + return rdata; +} + +void pmic_config_interface(u32 reg, u32 val, u32 mask, u32 shift) +{ + u32 old, new; + + pwrap_read(reg, &old); + + new = old & ~(mask << shift); + new |= (val << shift); + pwrap_write(reg, new); + + DEBUG_PMIC("[%s] write Reg[%#x]=%#x -> %#x\n", + __func__, reg, old, new); +} + +static void mt6358_init_setting(void) +{ + pmic_read_interface(PMIC_SWCID, 0xFFFF, 0); + pmic_config_interface(PMIC_TOP_RST_MISC_SET, 0x0020, 0xFFFF, 0); //[5]=1, RG_WDTRSTB_DEB + pmic_config_interface(PMIC_TOP_RST_MISC_CLR, 0x0002, 0xFFFF, 0); //[1]=0, RG_WDTRSTB_MODE + pmic_config_interface(PMIC_TOP_RST_MISC_SET, 0x0001, 0xFFFF, 0); //[0]=1, RG_WDTRSTB_EN + pmic_read_interface(PMIC_TOP_RST_MISC, 0xFFFF, 0); + + /* write TMA KEY with magic number */ + pmic_config_interface(PMIC_TOP_TMA_KEY, 0x9CA7, 0xFFFF, 0); + /* set VPROC12 sequence to VA12 */ + pmic_config_interface(PMIC_CPSDSA4, 0xA, 0x1F, 0); + pmic_config_interface(PMIC_TOP_TMA_KEY, 0x0, 0xFFFF, 0); +} + +void mt6358_init(void) +{ + if (pwrap_init()) + die("ERROR - Failed to initial pmic wrap!"); + + mt6358_init_setting(); +} diff --git a/src/soc/mediatek/mt8183/pmic_wrap.c b/src/soc/mediatek/mt8183/pmic_wrap.c new file mode 100644 index 0000000..bb3cf57 --- /dev/null +++ b/src/soc/mediatek/mt8183/pmic_wrap.c @@ -0,0 +1,691 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2018 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <stddef.h> +#include <timer.h> + +#include <soc/addressmap.h> +#include <soc/pll.h> +#include <soc/infracfg.h> +#include <soc/pmic_wrap.h> + +#define PWRAPTAG "[PWRAP] " +#define pwrap_log(fmt, arg ...) printk(BIOS_INFO, PWRAPTAG fmt, ## arg) +#define pwrap_err(fmt, arg ...) printk(BIOS_ERR, PWRAPTAG \ + "ERROR,line=%d" fmt, __LINE__, ## arg) + +typedef u32 (*loop_condition_fp)(u32); + +static inline u32 wait_for_fsm_idle(u32 x) +{ + return ((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != + WACS_FSM_IDLE; +} +static inline u32 wait_for_fsm_vldclr(u32 x) +{ + return ((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != + WACS_FSM_WFVLDCLR; +} + +static inline u32 wait_for_sync(u32 x) +{ + return ((x >> RDATA_SYNC_IDLE_SHIFT) & RDATA_SYNC_IDLE_MASK) != + WACS_SYNC_IDLE; +} + +static inline u32 wait_for_idle_and_sync(u32 x) +{ + return ((((x >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) != + WACS_FSM_IDLE) || (((x >> RDATA_SYNC_IDLE_SHIFT) & + RDATA_SYNC_IDLE_MASK)!= WACS_SYNC_IDLE)); +} + +static inline u32 wait_for_state_idle(loop_condition_fp fp, u32 timeout_us, + u32 *wacs_register, u32 *wacs_vldclr_register, u32 *read_reg) +{ + u32 reg_rdata; + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, timeout_us); + do { + reg_rdata = WRAP_RD32(wacs_register); + switch ((reg_rdata >> RDATA_WACS_FSM_SHIFT) & RDATA_WACS_FSM_MASK) { + case WACS_FSM_WFVLDCLR: + WRAP_WR32(wacs_vldclr_register, 1); + pwrap_log("WACS_FSM = VLDCLR\n"); + break; + case WACS_FSM_WFDLE: + pwrap_log("WACS_FSM = WFDLE\n"); + break; + case WACS_FSM_REQ: + pwrap_log("WACS_FSM = REQ\n"); + break; + default: + break; + } + + if (stopwatch_expired(&sw)) { + pwrap_err("timeout when waiting for idle\n"); + return E_PWR_WAIT_IDLE_TIMEOUT; + } + } while (fp(reg_rdata)); + if (read_reg) + *read_reg = reg_rdata; + + return 0; +} + +static inline u32 wait_for_state_ready(loop_condition_fp fp, u32 timeout_us, + u32 *wacs_register, u32 *read_reg) +{ + u32 reg_rdata; + struct stopwatch sw; + + stopwatch_init_usecs_expire(&sw, timeout_us); + do { + reg_rdata = WRAP_RD32(wacs_register); + + if (stopwatch_expired(&sw)) { + pwrap_err("timeout when waiting for ready\n"); + return E_PWR_WAIT_IDLE_TIMEOUT; + } + } while (fp(reg_rdata)); + if (read_reg) + *read_reg = reg_rdata; + + return 0; +} + +static s32 pwrap_wacs2(u32 write, u32 adr, + u32 wdata, u32 *rdata, u32 init_check) +{ + u32 reg_rdata = 0; + u32 wacs_write = 0; + u32 wacs_adr = 0; + u32 wacs_cmd = 0; + u32 return_value = 0; + + /* Check argument validation */ + if ((write & ~(0x1)) != 0) + return E_PWR_INVALID_RW; + if ((adr & ~(0xffff)) != 0) + return E_PWR_INVALID_ADDR; + if ((wdata & ~(0xffff)) != 0) + return E_PWR_INVALID_WDAT; + + if (init_check) { + reg_rdata = WRAP_RD32(&mt8183_pwrap->wacs2_rdata); + /* Prevent someone to used pwrap before pwrap init */ + if (((reg_rdata >> RDATA_INIT_DONE_SHIFT) + & RDATA_INIT_DONE_MASK) != WACS_INIT_DONE) { + pwrap_err("initialization isn't finished\n"); + return E_PWR_NOT_INIT_DONE; + } + } + + /* Check IDLE & INIT_DONE in advance */ + return_value = + wait_for_state_idle(wait_for_fsm_idle, TIMEOUT_WAIT_IDLE_US, + &mt8183_pwrap->wacs2_rdata, &mt8183_pwrap->wacs2_vldclr, 0); + + if (return_value != 0) { + pwrap_err("wait_for_fsm_idle fail,return_value=%d\n", + return_value); + return E_PWR_WAIT_IDLE_TIMEOUT; + } + + wacs_write = write << 31; + wacs_adr = (adr >> 1) << 16; + wacs_cmd = wacs_write | wacs_adr | wdata; + + WRAP_WR32(&mt8183_pwrap->wacs2_cmd, wacs_cmd); + if (write == 0) { + if (NULL == rdata) { + pwrap_err("rdata is a NULL pointer\n"); + return E_PWR_INVALID_ARG; + } + + return_value = + wait_for_state_ready(wait_for_fsm_vldclr, TIMEOUT_READ_US, + &mt8183_pwrap->wacs2_rdata, ®_rdata); + + if (return_value != 0) { + pwrap_err("wait_for_fsm_vldclr fail,return_value=%d\n", + return_value); + return E_PWR_WAIT_IDLE_TIMEOUT_READ; + } + + *rdata = (reg_rdata >> RDATA_WACS_RDATA_SHIFT) + & RDATA_WACS_RDATA_MASK; + WRAP_WR32(&mt8183_pwrap->wacs2_vldclr, 1); + } + + return return_value; +} + +s32 pwrap_read(u32 adr, u32 *rdata) +{ + return pwrap_wacs2(0,adr,0,rdata, 1); +} + +s32 pwrap_write(u32 adr, u32 wdata) +{ + return pwrap_wacs2(1,adr,wdata,0, 1); +} + +static s32 pwrap_read_nochk(u32 adr, u32 *rdata) +{ + return pwrap_wacs2(0, adr, 0, rdata, 0); +} + +static s32 pwrap_write_nochk(u32 adr, u32 wdata) +{ + return pwrap_wacs2(1, adr, wdata, 0, 0); +} + +static void pwrap_soft_reset(void) +{ + WRAP_WR32(&mt8183_infracfg->infra_globalcon_rst2_set, 0x1); + WRAP_WR32(&mt8183_infracfg->infra_globalcon_rst2_clr, 0x1); +} + +static void pwrap_spi_clk_set(void) +{ + WRAP_WR32(&mtk_topckgen->clk_cfg_5_clr, 0x93000000); + WRAP_WR32(&mtk_topckgen->clk_cfg_5_set, 0x1 << 24); + WRAP_WR32(&mtk_topckgen->clk_cfg_update, 0x1 << 23); + + WRAP_WR32(&mt8183_infracfg->module_sw_cg_0_set, 0x0000000F); + WRAP_WR32(&mt8183_infracfg->module_sw_cg_2_set, 0x00000100); + + pwrap_soft_reset(); + + WRAP_WR32(&mt8183_infracfg->module_sw_cg_0_clr, 0x0000000F); + WRAP_WR32(&mt8183_infracfg->module_sw_cg_2_clr, 0x00000100); +} + +static s32 pwrap_init_dio(u32 dio_en) +{ + u32 rdata = 0x0; + + pwrap_write_nochk(PMIC_DEW_DIO_EN, dio_en); + do { + rdata = WRAP_RD32(&mt8183_pwrap->wacs2_rdata); + } while (wait_for_idle_and_sync(rdata)); + + WRAP_WR32(&mt8183_pwrap->dio_en, dio_en); + return 0; +} + +static void pwrap_lock_SPISLVReg(void) +{ + pwrap_write_nochk(PMIC_SPISLV_KEY, 0x0); +} + +static void pwrap_InitStaUpd(void) +{ + WRAP_WR32(&mt8183_pwrap->staupd_grpen, 0xf5); + + /* CRC */ + pwrap_write_nochk(PMIC_DEW_CRC_EN, 0x1); + WRAP_WR32(&mt8183_pwrap->crc_en, 0x1); + WRAP_WR32(&mt8183_pwrap->sig_adr, PMIC_DEW_CRC_VAL); + + WRAP_WR32(&mt8183_pwrap->eint_sta0_adr, PMIC_CPU_INT_STA); + + /* MD ADC Interface */ + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_latest_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_wp_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_0_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_1_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_2_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_3_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_4_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_5_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_6_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_7_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_8_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_9_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_10_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_11_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_12_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_13_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_14_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_15_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_16_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_17_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_18_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_19_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_20_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_21_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_22_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_23_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_24_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_25_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_26_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_27_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_28_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_29_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_30_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + WRAP_WR32(&mt8183_pwrap->md_auxadc_rdata_31_addr, + (PMIC_AUXADC_ADC35 << 16) + PMIC_AUXADC_ADC31); + + WRAP_WR32(&mt8183_pwrap->int_gps_auxadc_cmd_addr, + (PMIC_AUXADC_RQST1 << 16) + PMIC_AUXADC_RQST0); + WRAP_WR32(&mt8183_pwrap->int_gps_auxadc_cmd, (0x0040 << 16) + 0x0080); + WRAP_WR32(&mt8183_pwrap->int_gps_auxadc_rdata_addr, + (PMIC_AUXADC_ADC32 << 16) + PMIC_AUXADC_ADC17); + + WRAP_WR32(&mt8183_pwrap->ext_gps_auxadc_rdata_addr, PMIC_AUXADC_ADC31); +} + +static void pwrap_starve_set(void) +{ + WRAP_WR32(&mt8183_pwrap->harb_hprio, 0xf); + WRAP_WR32(&mt8183_pwrap->starv_counter_0 , 0x402); + WRAP_WR32(&mt8183_pwrap->starv_counter_1 , 0x403); + WRAP_WR32(&mt8183_pwrap->starv_counter_2 , 0x403); + WRAP_WR32(&mt8183_pwrap->starv_counter_3 , 0x403); + WRAP_WR32(&mt8183_pwrap->starv_counter_4 , 0x40f); + WRAP_WR32(&mt8183_pwrap->starv_counter_5 , 0x420); + WRAP_WR32(&mt8183_pwrap->starv_counter_6 , 0x428); + WRAP_WR32(&mt8183_pwrap->starv_counter_7 , 0x428); + WRAP_WR32(&mt8183_pwrap->starv_counter_8 , 0x413); + WRAP_WR32(&mt8183_pwrap->starv_counter_9 , 0x417); + WRAP_WR32(&mt8183_pwrap->starv_counter_10, 0x417); + WRAP_WR32(&mt8183_pwrap->starv_counter_11, 0x47c); + WRAP_WR32(&mt8183_pwrap->starv_counter_12, 0x47c); + WRAP_WR32(&mt8183_pwrap->starv_counter_13, 0x740); + WRAP_WR32(&mt8183_pwrap->starv_counter_16, 0x740); +} + +static void pwrap_enable(void) +{ + WRAP_WR32(&mt8183_pwrap->hprio_arb_en, 0x3fa75); + WRAP_WR32(&mt8183_pwrap->wacs0_en, 0x1); + WRAP_WR32(&mt8183_pwrap->wacs2_en, 0x1); + WRAP_WR32(&mt8183_pwrap->wacs_p2p_en, 0x1); + WRAP_WR32(&mt8183_pwrap->wacs_md32_en, 0x1); + /* 100us */ + WRAP_WR32(&mt8183_pwrap->staupd_ctrl, 0x5); + WRAP_WR32(&mt8183_pwrap->wdt_unit, 0xf); + WRAP_WR32(&mt8183_pwrap->wdt_src_en_0, 0xffffffff); + WRAP_WR32(&mt8183_pwrap->wdt_src_en_1, 0xffffffff); + WRAP_WR32(&mt8183_pwrap->timer_en, 0x1); + WRAP_WR32(&mt8183_pwrap->int0_en, 0xffffffff); + /* disable Matching interrupt for bit 28 */ + WRAP_WR32(&mt8183_pwrap->int1_en, 0xeef7ffff); +} + +static s32 pwrap_init_sistrobe(int dual_si_sample_settings) +{ + u32 rdata; + int si_en_sel, si_ck_sel, si_dly, si_sample_ctrl, i, error = 0; + char result_faulty = 0, found; + int test_data[30] = { + 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, 0x9669, 0x6996, + 0x9669, 0x6996, 0x9669, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, + 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x5AA5, 0xA55A, 0x1B27, + 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, 0x1B27, + 0x1B27, 0x1B27}; + + found = 0; + for (si_en_sel = 0; si_en_sel < 8; si_en_sel++) { + for (si_ck_sel = 0; si_ck_sel < 2; si_ck_sel++) { + si_sample_ctrl = (si_en_sel << 6) | (si_ck_sel << 5); + WRAP_WR32(&mt8183_pwrap->si_sample_ctrl, si_sample_ctrl); + + pwrap_read_nochk(PMIC_DEW_READ_TEST, &rdata); + if (rdata == DEFAULT_VALUE_READ_TEST) { + pwrap_log("[DrvPWRAP_InitSiStrobe]The First Valid Sampling Clock Edge Is Found !!!\n"); + pwrap_log("found si_en_sel = %x, si_ck_sel = %x, si_sample_ctrl = %x, rdata = %x\n", + si_en_sel, si_ck_sel, si_sample_ctrl, rdata); + found = 1; + break; + } + } + if (found == 1) + break; + } + if (found == 0) { + result_faulty |= 0x1; + pwrap_err("result_faulty = %d\n", result_faulty); + } + if((si_en_sel == 7) && (si_ck_sel == 1)) { + result_faulty |= 0x2; + pwrap_err("result_faulty = %d (Sampling Clock is last Setting, can not Use)\n", result_faulty); + } + + for (si_dly = 0; si_dly < 10; si_dly++) { + pwrap_write_nochk(PMIC_RG_SPI_CON2, si_dly); + + error = 0; + for (i = 0; i < 30; i++) + { + pwrap_write_nochk(PMIC_DEW_WRITE_TEST, test_data[i]); + pwrap_read_nochk(PMIC_DEW_WRITE_TEST, &rdata); + if ((rdata & 0x7fff) != (test_data[i] & 0x7fff)) { + pwrap_log("InitSiStrobe (%x, %x, %x) Data Boundary Is Found !!\n", + si_dly, si_dly, rdata); + error = 1; + break; + } + } + if (error == 1) + break; + } + + /* TINFO = "[DrvPWRAP_InitSiStrobe] Change The Sampling Clock Edge To The Next One." */ + si_sample_ctrl = si_sample_ctrl + 0x20; + WRAP_WR32(&mt8183_pwrap->si_sample_ctrl, si_sample_ctrl); + if (si_dly == 10) { + pwrap_log("SI Strobe Calibration For PMIC 0 Done, (%x, si_dly = %x)\n", si_sample_ctrl, si_dly); + si_dly--; + } + pwrap_log("SI Strobe Calibration For PMIC 0 Done, (%x, %x)\n", si_sample_ctrl, si_dly); + + if (result_faulty != 0) + return result_faulty; + + /* Read Test */ + pwrap_read_nochk(PMIC_DEW_READ_TEST, &rdata); + if (rdata != DEFAULT_VALUE_READ_TEST) { + pwrap_err("pwrap_init_sistrobe Read Test Failed, rdata = %x, exp = 0x5aa5\n", rdata); + return 0x10; + } + pwrap_log("pwrap_init_sistrobe Read Test ok\n"); + + return 0; +} + +static void pwrap_InitSPISLV(void) +{ + pwrap_write_nochk(PMIC_FILTER_CON0, 0xf0); /* turn on IO filter function */ + pwrap_write_nochk(PMIC_SMT_CON1, 0xf); /* turn on IO SMT function to improve noise immunity */ + pwrap_write_nochk(PMIC_GPIO_PULLEN0_CLR, 0xf0); /* turn off IO pull function for power saving */ + pwrap_write_nochk(PMIC_RG_SPI_CON0, 0x1); /* turn off IO pull function for power saving */ + pwrap_write_nochk(PMIC_DRV_CON1, 0x8888); /* set PMIC GPIO driving current to 4mA */ +} + +static s32 pwrap_reset_spislv(void) +{ + u32 ret = 0; + u32 return_value = 0; + + WRAP_WR32(&mt8183_pwrap->hprio_arb_en, 0x0); + WRAP_WR32(&mt8183_pwrap->wrap_en, 0x0); + WRAP_WR32(&mt8183_pwrap->mux_sel, 0x1); + WRAP_WR32(&mt8183_pwrap->man_en, 0x1); + WRAP_WR32(&mt8183_pwrap->dio_en, 0x0); + + WRAP_WR32(&mt8183_pwrap->man_cmd, (OP_WR << 13) | (OP_CSL << 8)); + WRAP_WR32(&mt8183_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); + WRAP_WR32(&mt8183_pwrap->man_cmd, (OP_WR << 13) | (OP_CSH << 8)); + WRAP_WR32(&mt8183_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); + WRAP_WR32(&mt8183_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); + WRAP_WR32(&mt8183_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); + WRAP_WR32(&mt8183_pwrap->man_cmd, (OP_WR << 13) | (OP_OUTS << 8)); + + return_value = + wait_for_state_ready(wait_for_sync, TIMEOUT_WAIT_IDLE_US, + &mt8183_pwrap->wacs2_rdata, 0); + + if (return_value != 0) { + pwrap_err("reset_spislv fail,ret=%x\n", return_value); + ret = E_PWR_TIMEOUT; + } + + WRAP_WR32(&mt8183_pwrap->man_en, 0x0); + WRAP_WR32(&mt8183_pwrap->mux_sel, 0x0); + + return ret; +} + +static void pwrap_init_reg_clock(u32 regck_sel) +{ + WRAP_WR32(&mt8183_pwrap->ext_ck_write, 0x1); + + pwrap_write_nochk(PMIC_DEW_RDDMY_NO, 0x8); + WRAP_WR32(&mt8183_pwrap->rddmy, 0x8); + + /* Config SPI Waveform according to reg clk */ + if (regck_sel == 1) { + WRAP_WR32(&mt8183_pwrap->cshext_write, 0x0); + WRAP_WR32(&mt8183_pwrap->cshext_read, 0x0); + WRAP_WR32(&mt8183_pwrap->cslext_write, 0x0); + WRAP_WR32(&mt8183_pwrap->cslext_read, 0x0); + } else { /*Safe Mode*/ + WRAP_WR32(&mt8183_pwrap->cshext_write, 0x0f0f); + WRAP_WR32(&mt8183_pwrap->cshext_read, 0x0f0f); + WRAP_WR32(&mt8183_pwrap->cslext_write, 0x0f0f); + WRAP_WR32(&mt8183_pwrap->cslext_read, 0x0f0f); + } +} + + +static int pwrap_wacs2_write_test(int pmic_no) +{ + u32 rdata; + + if (pmic_no == 0) { + pwrap_write_nochk(PMIC_DEW_WRITE_TEST, 0xa55a); + pwrap_read_nochk(PMIC_DEW_WRITE_TEST, &rdata); + if (rdata != 0xa55a) { + pwrap_err("Error: w_rdata = %x, exp = 0xa55a\n", rdata); + return E_PWR_WRITE_TEST_FAIL; + } + } + + return 0; +} + +s32 pwrap_init(void) +{ + static s32 init = -1; + s32 sub_return = 0; + u32 rdata; + + if (init > 0) { + pwrap_log("pwrap_init already initialize\n"); + return 0; + } + + pwrap_log("pwrap_init start\n"); + + pwrap_spi_clk_set(); + + pwrap_log("pwrap_spi_clk_set ok\n"); + + /* Enable DCM */ + pwrap_log("Not need to enable DCM\n"); + + /* Reset SPISLV */ + sub_return = pwrap_reset_spislv(); + if (sub_return != 0) { + pwrap_err("reset_spislv fail,ret=%x\n", sub_return); + return E_PWR_INIT_RESET_SPI; + } + pwrap_log("Reset SPISLV ok\n"); + + /* Enable WRAP */ + WRAP_WR32(&mt8183_pwrap->wrap_en, 0x1); + pwrap_log("Enable WRAP ok\n"); + + /* Enable WACS2 */ + WRAP_WR32(&mt8183_pwrap->wacs2_en, 0x1); + WRAP_WR32(&mt8183_pwrap->hprio_arb_en, 0x4); /* ONLY WACS2 */ + + pwrap_log("Enable WACS2 ok\n"); + + /* SPI Waveform Configuration. 0:safe mode, 1:18MHz */ + pwrap_init_reg_clock(1); + pwrap_log("init_reg_clock ok\n"); + + pwrap_log("pwrap_init_reg_clock ok\n"); + + /* SPI Slave Configuration */ + pwrap_InitSPISLV(); + pwrap_log("InitSPISLV ok\n"); + + /* Enable DIO mode */ + sub_return = pwrap_init_dio(1); + if (sub_return != 0) { + pwrap_err("dio test error,err=%x, ret=%x\n", 0x11, sub_return); + return E_PWR_INIT_DIO; + } + pwrap_log("pwrap_init_dio ok\n"); + + /* Input data calibration flow; */ + sub_return = pwrap_init_sistrobe(0); + if (sub_return != 0) { + pwrap_err("InitSiStrobe fail,ret=%x\n", sub_return); + return E_PWR_INIT_SIDLY; + } + pwrap_log("pwrap_init_sistrobe ok\n"); + + /* Write test using WACS2. check Write test default value */ + sub_return = pwrap_wacs2_write_test(0); + if (sub_return != 0) { + pwrap_err("write test 0 fail\n"); + return E_PWR_INIT_WRITE_TEST; + } + + pwrap_log("pwrap_wacs2_write_test ok\n"); + + /* Status update function initialization + * 1. Signature Checking using CRC (CRC 0 only) + * 2. EINT update + * 3. Read back Auxadc thermal data for GPS + */ + pwrap_InitStaUpd(); + pwrap_log("pwrap_InitStaUpd ok\n"); + + WRAP_WR32(&mt8183_pwrap->priority_user_sel_2, 0x0b09080a); + WRAP_WR32(&mt8183_pwrap->arbiter_out_sel_2, 0x0b080a09); + + pwrap_starve_set(); + pwrap_log("pwrap_starve_set ok\n"); + + pwrap_enable(); + pwrap_log("pwrap_enable ok\n"); + + /* Initialization Done */ + WRAP_WR32(&mt8183_pwrap->init_done0, 0x1); + WRAP_WR32(&mt8183_pwrap->init_done2, 0x1); + WRAP_WR32(&mt8183_pwrap->init_done_p2p, 0x1); + WRAP_WR32(&mt8183_pwrap->init_done_md32, 0x1); + + /* Lock SPISLV Registers */ + pwrap_lock_SPISLVReg(); + pwrap_log("Lock SPI SLV Reg ok\n"); + + pwrap_log("pwrap_init Done\n"); + + /* Read Last three command */ + pwrap_read_nochk(PMIC_RG_SPI_CON3, &rdata); + pwrap_log("RECORD_CMD0:0x%x (The last command addr)\n", (rdata & 0x3fff)); + pwrap_read_nochk(PMIC_RG_SPI_CON6, &rdata); + pwrap_log("RECORD_WDATA0:0x%x (The last command wdata)\n", rdata); + pwrap_read_nochk(PMIC_RG_SPI_CON4, &rdata); + pwrap_log("RECORD_CMD1:0x%x (The second-last command addr)\n", (rdata & 0x3fff)); + pwrap_read_nochk(PMIC_RG_SPI_CON7, &rdata); + pwrap_log("RECORD_WDATA1:0x%x (The second-last command wdata)\n", rdata); + pwrap_read_nochk(PMIC_RG_SPI_CON5, &rdata); + pwrap_log("RECORD_CMD2:0x%x (The third-last command addr)\n", (rdata & 0x3fff)); + pwrap_read_nochk(PMIC_RG_SPI_CON8, &rdata); + pwrap_log("RECORD_WDATA2:0x%x (The third-last command wdata)\n", rdata); + + /* Enable Command Recording */ + sub_return = pwrap_write_nochk(PMIC_RG_SPI_RECORD0, 0x1); + if (sub_return != 0) + pwrap_err("enable spi debug fail, ret=%x\n", sub_return); + pwrap_log("enable spi debug ok\n"); + + /* Clear Last three command */ + sub_return = pwrap_write_nochk(PMIC_RG_SPI_CON13, 0x1); + if (sub_return != 0) + pwrap_err("clear record command fail, ret=%x\n", sub_return); + sub_return = pwrap_write_nochk(PMIC_RG_SPI_CON13, 0x0); + if (sub_return != 0) + pwrap_err("clear record command fail, ret=%x\n", sub_return); + pwrap_log("clear record command ok\n\r"); + + pwrap_log("GPS_CMD_ADDR:0x%x, GPS_CMD:0x%x, GPS_RDATA_ADDR:0x%x\n", + WRAP_RD32(&mt8183_pwrap->int_gps_auxadc_cmd_addr), + WRAP_RD32(&mt8183_pwrap->int_gps_auxadc_cmd), + WRAP_RD32(&mt8183_pwrap->int_gps_auxadc_rdata_addr)); + pwrap_log("GPSINF_0_STA:0x%x, GPSINF_1_STA:0x%x\n", + WRAP_RD32(&mt8183_pwrap->gpsinf_0_sta), + WRAP_RD32(&mt8183_pwrap->gpsinf_1_sta)); + + /* enable logging mode */ + pwrap_log("PMIC_WRAP_MONITOR_MODE = Logging Mode\n"); + WRAP_WR32(&mt8183_pwrap->monitor_ctrl_1, 0x1feff); /* disable monitor MD HW channel (CH8) */ + WRAP_WR32(&mt8183_pwrap->monitor_ctrl_2, 0x0); /* record all addr (mask+addr) */ + WRAP_WR32(&mt8183_pwrap->monitor_ctrl_3, 0x0); /* record all wdata (mask+addr) */ + WRAP_WR32(&mt8183_pwrap->monitor_ctrl_0, 0x8); /* clear log */ + WRAP_WR32(&mt8183_pwrap->monitor_ctrl_0, 0x1); /* reenable (Matching mode and Continue recording after interrupt trigger) */ + pwrap_log("monitor_ctrl_0 = 0x%x\n", WRAP_RD32(&mt8183_pwrap->monitor_ctrl_0)); + pwrap_log("monitor_ctrl_1 = 0x%x\n", WRAP_RD32(&mt8183_pwrap->monitor_ctrl_1)); + pwrap_log("monitor_ctrl_2 = 0x%x\n", WRAP_RD32(&mt8183_pwrap->monitor_ctrl_2)); + pwrap_log("monitor_ctrl_3 = 0x%x\n", WRAP_RD32(&mt8183_pwrap->monitor_ctrl_3)); + + pwrap_read_nochk(PMIC_PPCCTL0, &rdata); + rdata |= 0x1; + pwrap_write_nochk(PMIC_PPCCTL0, rdata); + rdata = 0; + pwrap_read_nochk(PMIC_PPCCTL0, &rdata); + if (rdata != 0x1) + pwrap_err("PWRHOLD=%x(should be 1)\n", rdata); + + init = 1; + + return 0; +} \ No newline at end of file diff --git a/src/soc/mediatek/mt8183/soc.c b/src/soc/mediatek/mt8183/soc.c index b51e7d4..1192f20 100644 --- a/src/soc/mediatek/mt8183/soc.c +++ b/src/soc/mediatek/mt8183/soc.c @@ -16,9 +16,9 @@ #include <device/device.h> #include <soc/emi.h> #include <soc/mmu_operations.h> +#include <soc/mt6358.h> #include <symbols.h>
- static void soc_read_resources(struct device *dev) { ram_resource(dev, 0, (uintptr_t)_dram / KiB, sdram_size() / KiB); @@ -27,6 +27,7 @@ static void soc_init(struct device *dev) { mtk_mmu_disable_l2c_sram(); + mt6358_init(); }
static struct device_operations soc_ops = {