Angel Pons has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36700 )
Change subject: sb/intel/i82801gx: Add common LPC decode code ......................................................................
Patch Set 5: Code-Review+2
(3 comments)
https://review.coreboot.org/c/coreboot/+/36700/5/src/mainboard/gigabyte/ga-9... File src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/36700/5/src/mainboard/gigabyte/ga-9... PS5, Line 82: ??? A comment says this is SuperIO Power Management Events. I guess the "???" means that the SIO datasheet doesn't mention such a thing?
https://review.coreboot.org/c/coreboot/+/36700/5/src/mainboard/kontron/986lc... File src/mainboard/kontron/986lcd-m/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/36700/5/src/mainboard/kontron/986lc... PS5, Line 45: ?? A comment says "io 0x300 decode". I wonder what this would be useful for.
https://review.coreboot.org/c/coreboot/+/36700/5/src/southbridge/intel/i8280... File src/southbridge/intel/i82801gx/early_init.c:
https://review.coreboot.org/c/coreboot/+/36700/5/src/southbridge/intel/i8280... PS5, Line 48: pci_write_config32(d31f0, GEN1_DEC, config->gen1_dec);
so by default it writes 0? […]
Zero is a valid value, because the least significant bit is "enable". If it is zero, the range is not used.