Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/49021 )
Change subject: soc/intel/alderlake: Determine PCIe RP enable mask using device on/off status
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/49021/2//COMMIT_MSG
Commit Message:
https://review.coreboot.org/c/coreboot/+/49021/2//COMMIT_MSG@9
PS2, Line 9: This change uses the newly added helper function
: `pcie_rp_enable_mask()` to determine the mask of PCH and CPU PCIe root
: ports that are enabled by the mainboard instead of relying on
: PcieRpEnable[] config.
:
This CL is in the related chain.
eh, yes, but the commit message describes the commit, not the chain
--
To view, visit
https://review.coreboot.org/c/coreboot/+/49021
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: Idcc21d8028f51a221d639440db4cf5a4e095c632
Gerrit-Change-Number: 49021
Gerrit-PatchSet: 2
Gerrit-Owner: EricR Lai
ericr_lai@compal.corp-partner.google.com
Gerrit-Reviewer: Furquan Shaikh
furquan@google.com
Gerrit-Reviewer: Martin Roth
martinroth@google.com
Gerrit-Reviewer: Patrick Georgi
pgeorgi@google.com
Gerrit-Reviewer: Patrick Rudolph
siro@das-labor.org
Gerrit-Reviewer: Subrata Banik
subrata.banik@intel.com
Gerrit-Reviewer: Tim Wawrzynczak
twawrzynczak@chromium.org
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-CC: Michael Niewöhner
foss@mniewoehner.de
Gerrit-Comment-Date: Fri, 01 Jan 2021 11:17:52 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Michael Niewöhner
foss@mniewoehner.de
Comment-In-Reply-To: EricR Lai
ericr_lai@compal.corp-partner.google.com
Gerrit-MessageType: comment