Srinidhi N Kaushik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39315 )
Change subject: mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation ......................................................................
mb/intel/tglrvp: add CNVi ASL entry for dynamic SSDT generation
This changes uses drivers/intel/wifi chip for CNVi device and adds dynamic SSDT entires for CNVi
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board and check for SSDT entries for CNVi
Signed-off-by: Srinidhi N Kaushik srinidhi.n.kaushik@intel.com Change-Id: Icdbffa0c29c9e0849a6a99f8592b6f35c0bb3207 --- M src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb 1 file changed, 5 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/39315/1
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index d4b5a39..9506738 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -121,7 +121,11 @@ device pci 14.0 on end # USB3.1 xHCI 0xA0ED device pci 14.1 on end # USB3.1 xDCI 0xA0EE device pci 14.2 on end # Shared RAM 0xA0EF - device pci 14.3 off end # CNVi: WiFi 0xA0F0 - A0F3 + device pci 14.3 on + chip drivers/intel/wifi + register "wake" = "GPE0_PME_B0" + end + end # CNVi: WiFi 0xA0F0 - A0F3 device pci 15.0 on end # I2C0 0xA0E8 device pci 15.1 on end # I2C1 0xA0E9 device pci 15.2 on end # I2C2 0xA0EA