Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38861 )
Change subject: soc/tigerlake: Add IRQ header and ACPI support for JSP ......................................................................
Patch Set 1:
(7 comments)
https://review.coreboot.org/c/coreboot/+/38861/1/src/soc/intel/tigerlake/acp... File src/soc/intel/tigerlake/acpi/pci_irqs_jsl.asl:
https://review.coreboot.org/c/coreboot/+/38861/1/src/soc/intel/tigerlake/acp... PS1, Line 20: Nothpeak NorthPeak?
https://review.coreboot.org/c/coreboot/+/38861/1/src/soc/intel/tigerlake/acp... PS1, Line 25: SCS I see only SerialIO
https://review.coreboot.org/c/coreboot/+/38861/1/src/soc/intel/tigerlake/acp... PS1, Line 52: , HECI4 configuration?
https://review.coreboot.org/c/coreboot/+/38861/1/src/soc/intel/tigerlake/acp... PS1, Line 63: , SPI2 IRQ configuration?
https://review.coreboot.org/c/coreboot/+/38861/1/src/soc/intel/tigerlake/acp... PS1, Line 75: Nothpeak NorthPeak?
https://review.coreboot.org/c/coreboot/+/38861/1/src/soc/intel/tigerlake/acp... PS1, Line 108: , No need to configure HECI4, SerialIO, eMMC and Graphics?
https://review.coreboot.org/c/coreboot/+/38861/1/src/soc/intel/tigerlake/inc... File src/soc/intel/tigerlake/include/soc/irq_jsl.h:
https://review.coreboot.org/c/coreboot/+/38861/1/src/soc/intel/tigerlake/inc... PS1, Line 18: Where does the information in this file come from? Is it captured in some document like EDS or FAS?