[coreboot-gerrit] Change in ...coreboot[master]: soc/intel/cannonlake: Configure SPI CS parameters in FSP UPD.

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/32791 )

Change subject: soc/intel/cannonlake: Configure SPI CS parameters in FSP UPD.
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Patch Set 5:

(2 comments)

https://review.coreboot.org/#/c/32791/5/src/soc/intel/cannonlake/fsp_params.... 
File src/soc/intel/cannonlake/fsp_params.c:

https://review.coreboot.org/#/c/32791/5/src/soc/intel/cannonlake/fsp_params.... 
PS5, Line 137: 			/* GSPI driver assumes CS0 is used */
Is this why we're only passing index 0 for the CsEnable and CsOutput? If so, please add a comment below at the call site as well for the assumptions being made.

https://review.coreboot.org/#/c/32791/5/src/soc/intel/cannonlake/fsp_params.... 
PS5, Line 403: (
fwiw, the parens aren't needed