Hello Wonkyu Kim, Caveh Jalali, Nick Vaccaro,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/39370
to review the following change.
Change subject: mb/google/volteer: Add support for pmc core driver ......................................................................
mb/google/volteer: Add support for pmc core driver
This patch adds INT33A1 device in dsdt to support PMC core driver.
BUG=b:146236297 BRANCH=none TEST="Build and flash volteer and verify it boots to kernel. Checked for valid files under /sys/kernel/debug/pmc_core."
Change-Id: Ib4edc7b636725177d508b62d15633534e9f44236 Signed-off-by: Venkata Krishna Nimmagadda venkata.krishna.nimmagadda@intel.com Reviewed-on: https://chrome-internal-review.googlesource.com/c/chromeos/third_party/coreb... Reviewed-by: Venkata Krishna Nimmagadda venkata.krishna.nimmagadda@intel.corp-partner.google.com Reviewed-by: Wonkyu Kim wonkyu.kim@intel.corp-partner.google.com Reviewed-by: Caveh Jalali caveh@google.com Reviewed-by: Nick Vaccaro nvaccaro@google.com Tested-by: Venkata Krishna Nimmagadda venkata.krishna.nimmagadda@intel.corp-partner.google.com Commit-Queue: Alex Levin levinale@google.com --- A src/soc/intel/common/acpi/pmc.asl M src/soc/intel/tigerlake/acpi/southbridge.asl 2 files changed, 40 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/39370/1
diff --git a/src/soc/intel/common/acpi/pmc.asl b/src/soc/intel/common/acpi/pmc.asl new file mode 100644 index 0000000..d576481 --- /dev/null +++ b/src/soc/intel/common/acpi/pmc.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2020 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device (PEPD) +{ + Name (_HID, "INT33A1" /* Intel Power Engine */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0D80") /* System Power Management Controller */) // _CID: Compatible ID + Name (_UID, One) // _UID: Unique ID + Name (PPD0, Package (0x03) + { + "\_SB.PCI0.SAT0", + Zero, + Package (0x02) + { + Zero, + Package (0x03) + { + 0xFF, + Zero, + 0x81 + } + } + }) +} + diff --git a/src/soc/intel/tigerlake/acpi/southbridge.asl b/src/soc/intel/tigerlake/acpi/southbridge.asl index 8593d07..1a198b0 100644 --- a/src/soc/intel/tigerlake/acpi/southbridge.asl +++ b/src/soc/intel/tigerlake/acpi/southbridge.asl @@ -51,3 +51,6 @@
/* PCI _OSC */ #include <soc/intel/common/acpi/pci_osc.asl> + +/* PMC Core*/ +#include <soc/intel/common/acpi/pmc.asl>