[coreboot-gerrit] Change in coreboot[master]: arch/x86: Cache the TSEG region at the top of ram

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34995 )

Change subject: arch/x86: Cache the TSEG region at the top of ram
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Patch Set 10:

(2 comments)

https://review.coreboot.org/c/coreboot/+/34995/9//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/34995/9//COMMIT_MSG@28 
PS9, Line 28: Signed-off-by: Kyösti Mälkki
> Remove my signed-off-by. […]

Done

https://review.coreboot.org/c/coreboot/+/34995/9/src/soc/amd/picasso/romstag... 
File src/soc/amd/picasso/romstage.c:

https://review.coreboot.org/c/coreboot/+/34995/9/src/soc/amd/picasso/romstag... 
PS9, Line 89: 	run_postcar_phase(&pcf);
> Everything about postcar in amd/picasso is wrong and work-in-progress. […]

CB:35025 was just referring to common API nothing new been done here.