Angel Pons has uploaded this change for review. ( https://review.coreboot.org/28231
Change subject: Documentation/northbridge/intel/sandybridge/*: fix typos ......................................................................
Documentation/northbridge/intel/sandybridge/*: fix typos
Fix some words' spelling and rename "Sandybridge" and "Ivybridge" in text (not filepaths) to match Intel's names "Sandy Bridge" and "Ivy Bridge".
Change-Id: Ic77126ccaf1d3ec5530a35d1a0f7d2ea5e174c9a Signed-off-by: Angel Pons th3fanbus@gmail.com --- M Documentation/northbridge/intel/sandybridge/nri.md M Documentation/northbridge/intel/sandybridge/nri_freq.md M Documentation/northbridge/intel/sandybridge/nri_read.md M Documentation/northbridge/intel/sandybridge/nri_registers.md 4 files changed, 15 insertions(+), 14 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/28231/1
diff --git a/Documentation/northbridge/intel/sandybridge/nri.md b/Documentation/northbridge/intel/sandybridge/nri.md index 1b07ba4..812cd23 100644 --- a/Documentation/northbridge/intel/sandybridge/nri.md +++ b/Documentation/northbridge/intel/sandybridge/nri.md @@ -3,7 +3,7 @@ ## Introduction
This documentation is intended to document the closed source memory controller -hardware for Intel 2nd Gen (Sandy Bride) and 3rd Gen (Ivy Bridge) core-i CPUs. +hardware for Intel 2nd Gen (Sandy Bridge) and 3rd Gen (Ivy Bridge) core-i CPUs.
The memory initialization code has to take care of lots of duties: 1. Selection of operating frequency @@ -41,13 +41,13 @@ ```
## (Inoffical) register documentation -- [Sandy Bride - Register documentation](nri_registers.md) +- [Sandy Bridge - Register documentation](nri_registers.md)
## Frequency selection -- [Sandy Bride - Frequency selection](nri_freq.md) +- [Sandy Bridge - Frequency selection](nri_freq.md)
## Read training -- [Sandy Bride - Read training](nri_read.md) +- [Sandy Bridge - Read training](nri_read.md)
### SMBIOS type 17 The SMBIOS specification allows to report the memory configuration in use. @@ -113,7 +113,7 @@
**Note:** This feature is available since coreboot 4.5
Try to swap memory modules and or try to use a different vendor. If nothing -helps you could have a look at capter [Debuggin] or report a ticket +helps you could have a look at chapter [Debugging] or report a ticket at [ticket.coreboot.org]. Please provide a full RAM init log, that has been captured using EHCI debug.
diff --git a/Documentation/northbridge/intel/sandybridge/nri_freq.md b/Documentation/northbridge/intel/sandybridge/nri_freq.md index d8b73b3..208c1cb 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_freq.md +++ b/Documentation/northbridge/intel/sandybridge/nri_freq.md @@ -1,7 +1,8 @@ # Frequency selection
## Introduction -This chapter explains the frequency selection done on Sandybride and Ivybridge. +This chapter explains the frequency selection done on Sandy Bridge and Ivy +Bridge memory initialization.
## Definitions ```eval_rst @@ -58,7 +59,7 @@
**Note:** Ignoring the fuses might cause system instability !
-On Sandy Bride *CAPID0_A* is being read, and on Ivybridge *CAPID0_B* is being +On Sandy Bridge *CAPID0_A* is being read, and on Ivy Bridge *CAPID0_B* is being read. coreboot reads those registers and honors the limit in case the Kconfig option `CONFIG_NATIVE_RAMINIT_IGNORE_MAX_MEM_FUSES` wasn't set. Power users that want to let their RAM run at DRAM's "stock" frequency need to @@ -84,7 +85,7 @@ By using this register it's possible to force a minimum operating frequency.
## Reference clock -While Sandybride supports 133 MHz reference clock (REFCK), Ivy Bridge also +While Sandy Bridge supports 133 MHz reference clock (REFCK), Ivy Bridge also supports 100 MHz reference clock. The reference clock is multiplied by the DRAM multiplier to select the DRAM frequency (SCK) by the following formula:
@@ -92,7 +93,7 @@
**Note:** Since coreboot 4.6 Ivy Bridge supports 100MHz REFCK.
-## Sandy Bride's supported frequencies +## Sandy Bridge's supported frequencies ```eval_rst +------------+-----------+------------------+-------------------------+---------------+ | SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment | @@ -111,7 +112,7 @@ +------------+-----------+------------------+-------------------------+---------------+ ```
-## Ivybridge's supported frequencies +## Ivy Bridge's supported frequencies ```eval_rst +------------+-----------+------------------+-------------------------+---------------+ | SCK [Mhz] | DDR [Mhz] | Mutiplier (MULT) | Reference clock (REFCK) | Comment | @@ -144,7 +145,7 @@
'1: since coreboot 4.6
## Multiplier selection -coreboot select the maximum frequency to operate at by the following formula: +coreboot selects the maximum frequency to operate at by the following formula: ``` if devicetree's max_mem_clock_mhz > 0: freq_max := max_mem_clock_mhz diff --git a/Documentation/northbridge/intel/sandybridge/nri_read.md b/Documentation/northbridge/intel/sandybridge/nri_read.md index 0496657..f5c79ac 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_read.md +++ b/Documentation/northbridge/intel/sandybridge/nri_read.md @@ -2,7 +2,7 @@
## Introduction
-This chapter explains the read training sequence done on Sandy Bride and +This chapter explains the read training sequence done on Sandy Bridge and Ivy Bridge memory initialization.
Read training is done to compensate the skew between DQS and SCK and to find diff --git a/Documentation/northbridge/intel/sandybridge/nri_registers.md b/Documentation/northbridge/intel/sandybridge/nri_registers.md index 601157c..6249560 100644 --- a/Documentation/northbridge/intel/sandybridge/nri_registers.md +++ b/Documentation/northbridge/intel/sandybridge/nri_registers.md @@ -1556,7 +1556,7 @@
*Width:* 16 Bit
-*Desc:* OTHP Workaround (SandyBridge only) Register, Channel 0 +*Desc:* OTHP Workaround (Sandy Bridge only) Register, Channel 0
```eval_rst +-----------+------------------------------------------------------------------+ @@ -2138,7 +2138,7 @@ | 0:7| Selected multiplier: 100Mhz [7,12], 133Mhz [3,19] | +-----------+------------------------------------------------------------------+ | 8 | - 1: 100Mhz reference clock | -| | - 0: 133Mhz reference clock (IvyBridge only) | +| | - 0: 133Mhz reference clock (Ivy Bridge only) | +-----------+------------------------------------------------------------------+ | 31 | PLL busy | +-----------+------------------------------------------------------------------+