HAOUAS Elyes has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/18548 )
Change subject: nb/intel/i945: Program CxODT value for each channel ......................................................................
Patch Set 30:
Patch Set 30:
Patch Set 30:
I've populated only channel 0 with 2 DIMMs as you can see, we have the message "C1ODT: Channel 1 has one DIMM." https://pastebin.com/9pxTYPQx The board boots but this patch does not what expected
That might happen if the SPD mapping is incorrect. That is, your mainboard settings might be saying that the SPD on CH1-S0 is for CH0-S1
Thx, but in posted log we can see "Setting up RAM controller. This mainboard supports Dual Channel Operation. Reading SPD using i2c block operation. DDR II Channel 0 Socket 0: x8DDS DIMM 0 side 0 = 1024 MB DIMM 0 side 1 = 1024 MB Reading SPD using i2c block operation. DDR II Channel 0 Socket 1: x8DDS DIMM 1 side 0 = 1024 MB DIMM 1 side 1 = 1024 MB DDR II Channel 1 Socket 0: N/A DDR II Channel 1 Socket 1: N/A Memory will be driven at 667MT with CAS=5 clocks tRAS = 15 cycles"
and when I check using vendor bios with only channel 0 populated (dimm0 + dimm1), the SPD are: 0x50 and 0x51.
NB (using vendor bios) : this board have 2 channels and 2 DIMMs per channel dimm0 at 0x50 dimm1 at 0x51 dimm2 at 0x52 dimm3 at 0x53