[coreboot-gerrit] [M] Change in coreboot[master]: soc/amd/stoneyridge: factor out P-state utils to link in all stages

[Felix Held (Code Review)]

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/74145 )

Change subject: soc/amd/stoneyridge: factor out P-state utils to link in all stages
......................................................................

soc/amd/stoneyridge: factor out P-state utils to link in all stages

tsc_freq.c gets built into all stages, but the tsc_freq_mhz function it
implements calls the get_pstate_0_reg function which was only built into
ramstage. Since tsc_freq_mhz was only called in ramstage, commit
2323acab6a7a ("soc/amd/stoneyridge: implement and use get_pstate_0_reg")
didn't cause the build to fail, but better factor out the P-state-
related utility functions into a separate compilation unit and include
it in all stages that also include tsc_freq.c.

Signed-off-by: Felix Held 
Change-Id: Id3a3ee218f495be5e60a888944487704e7e8a1a1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74145
Tested-by: build bot (Jenkins) 
Reviewed-by: Matt DeVillier 
Reviewed-by: Martin Roth 
---
M src/soc/amd/stoneyridge/Makefile.inc
M src/soc/amd/stoneyridge/cpu.c
A src/soc/amd/stoneyridge/pstate_util.c
3 files changed, 86 insertions(+), 54 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Matt DeVillier: Looks good to me, but someone else must approve
  Martin Roth: Looks good to me, approved

diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 1e8e794..65edea0 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -46,10 +46,12 @@
 ramstage-y += psp.c

all-y += monotonic_timer.c
+all-y += pstate_util.c
 all-y += reset.c
 all-y += tsc_freq.c
 all-y += uart.c

+smm-y += pstate_util.c
 smm-y += monotonic_timer.c
 smm-y += smihandler.c
 smm-y += tsc_freq.c
diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c
index c5c2f68..3aedd0e 100644
--- a/src/soc/amd/stoneyridge/cpu.c
+++ b/src/soc/amd/stoneyridge/cpu.c
@@ -4,7 +4,6 @@
 #include <amdblocks/iomap.h>
 #include <amdblocks/mca.h>
 #include <amdblocks/reset.h>
-#include <amdblocks/smn.h>
 #include <cpu/amd/msr.h>
 #include <cpu/cpu.h>
 #include <cpu/x86/mp.h>
@@ -15,7 +14,6 @@
 #include <soc/pci_devs.h>
 #include <soc/cpu.h>
 #include <soc/iomap.h>
-#include <soc/msr.h>
 #include <console/console.h>
 #include <types.h>

@@ -72,55 +70,3 @@
    .ops      = &cpu_dev_ops,
    .id_table = cpu_table,
 };
-
-uint32_t get_pstate_0_reg(void)
-{
-	return (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) >> 2) & 0x7;
-}
-
-static bool all_pstates_have_same_frequency_id(void)
-{
-	union pstate_msr pstate_reg;
-	size_t i;
-	bool first = true;
-	uint32_t frequency_id;
-
-	for (i = 0; i < 7; i++) {
-		pstate_reg.raw = rdmsr(PSTATE_MSR(i)).raw;
-
-		if (!pstate_reg.pstate_en)
-			continue;
-
-		if (first) {
-			frequency_id = pstate_reg.cpu_fid_0_5;
-			first = false;
-		} else if (frequency_id != pstate_reg.cpu_fid_0_5) {
-			return false;
-		}
-	}
-
-	return true;
-}
-
-#define CLK_PLL_LOCK_TIMER		0xD82220B8
-#define CLK_GATER_SEQUENCE_REGISTER	0xD8222114
-
-uint32_t get_pstate_latency(void)
-{
-	uint32_t latency = 0;
-	uint32_t smn_data;
-	uint32_t gaters_on_time, gaters_off_time;
-
-	smn_data = smn_read32(CLK_GATER_SEQUENCE_REGISTER);
-	gaters_on_time = (smn_data & 0xff) * 10;
-	gaters_off_time = (smn_data >> 8 & 0xff) * 10;
-	latency += DIV_ROUND_UP(15 * gaters_on_time, 1000);
-	latency += DIV_ROUND_UP(15 * gaters_off_time, 1000);
-
-	if (!all_pstates_have_same_frequency_id()) {
-		smn_data = smn_read32(CLK_PLL_LOCK_TIMER);
-		latency += DIV_ROUND_UP(smn_data & 0x1fff, 100);
-	}
-
-	return latency;
-}
diff --git a/src/soc/amd/stoneyridge/pstate_util.c b/src/soc/amd/stoneyridge/pstate_util.c
new file mode 100644
index 0000000..097a913
--- /dev/null
+++ b/src/soc/amd/stoneyridge/pstate_util.c
@@ -0,0 +1,62 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <amdblocks/cpu.h>
+#include <amdblocks/smn.h>
+#include <cpu/amd/msr.h>
+#include <cpu/x86/msr.h>
+#include <device/pci_ops.h>
+#include <soc/msr.h>
+#include <soc/pci_devs.h>
+#include <types.h>
+
+uint32_t get_pstate_0_reg(void)
+{
+	return (pci_read_config32(SOC_PM_DEV, CORE_PERF_BOOST_CTRL) >> 2) & 0x7;
+}
+
+static bool all_pstates_have_same_frequency_id(void)
+{
+	union pstate_msr pstate_reg;
+	size_t i;
+	bool first = true;
+	uint32_t frequency_id;
+
+	for (i = 0; i < 7; i++) {
+		pstate_reg.raw = rdmsr(PSTATE_MSR(i)).raw;
+
+		if (!pstate_reg.pstate_en)
+			continue;
+
+		if (first) {
+			frequency_id = pstate_reg.cpu_fid_0_5;
+			first = false;
+		} else if (frequency_id != pstate_reg.cpu_fid_0_5) {
+			return false;
+		}
+	}
+
+	return true;
+}
+
+#define CLK_PLL_LOCK_TIMER		0xD82220B8
+#define CLK_GATER_SEQUENCE_REGISTER	0xD8222114
+
+uint32_t get_pstate_latency(void)
+{
+	uint32_t latency = 0;
+	uint32_t smn_data;
+	uint32_t gaters_on_time, gaters_off_time;
+
+	smn_data = smn_read32(CLK_GATER_SEQUENCE_REGISTER);
+	gaters_on_time = (smn_data & 0xff) * 10;
+	gaters_off_time = (smn_data >> 8 & 0xff) * 10;
+	latency += DIV_ROUND_UP(15 * gaters_on_time, 1000);
+	latency += DIV_ROUND_UP(15 * gaters_off_time, 1000);
+
+	if (!all_pstates_have_same_frequency_id()) {
+		smn_data = smn_read32(CLK_PLL_LOCK_TIMER);
+		latency += DIV_ROUND_UP(smn_data & 0x1fff, 100);
+	}
+
+	return latency;
+}