Name of user not set #1004406 has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69798 )
Change subject: adds basic support for Raptorlake-S CPUs on Alderlake PCH (#640555) ......................................................................
adds basic support for Raptorlake-S CPUs on Alderlake PCH (#640555)
Change-Id: I767dd08a169a6af59188d9ecd73520b916f69155 Signed-off-by: Max Fritz antischmock@googlemail.com --- M 3rdparty/intel-microcode M src/include/cpu/intel/cpu_ids.h M src/include/device/pci_ids.h M src/soc/intel/alderlake/Kconfig M src/soc/intel/alderlake/Makefile.inc M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/cpu.c M src/soc/intel/alderlake/fsp_params.c M src/soc/intel/alderlake/include/soc/cpu.h M src/soc/intel/alderlake/vr_config.c M src/soc/intel/common/block/cpu/mp_init.c M src/soc/intel/common/block/systemagent/systemagent.c 13 files changed, 81 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/69798/1
diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 6c0c469..262f0c9 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 6c0c4691e5bb446e0e428ebca595164709c59586 +Subproject commit 262f0c97f2fbc3839a59523cc6c6bcf500e2850b diff --git a/src/include/cpu/intel/cpu_ids.h b/src/include/cpu/intel/cpu_ids.h index 381f20c..2a16f6f 100644 --- a/src/include/cpu/intel/cpu_ids.h +++ b/src/include/cpu/intel/cpu_ids.h @@ -64,6 +64,7 @@ #define CPUID_ALDERLAKE_N_A0 0xb06e0 #define CPUID_METEORLAKE_A0_1 0xa06a0 #define CPUID_METEORLAKE_A0_2 0xa06a1 +#define CPUID_RAPTORLAKE_S_S0 0xb0671 #define CPUID_RAPTORLAKE_P_J0 0xb06a2 #define CPUID_RAPTORLAKE_P_Q0 0xb06a3
diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index f1f77e0..c645a3b 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3989,10 +3989,10 @@ #define PCI_DID_INTEL_ADL_P_GT2_7 0x4628 #define PCI_DID_INTEL_ADL_P_GT2_8 0x46b1 #define PCI_DID_INTEL_ADL_P_GT2_9 0x4626 -#define PCI_DID_INTEL_ADL_S_GT1 0x4680 -#define PCI_DID_INTEL_ADL_S_GT1_1 0x4682 +#define PCI_DID_INTEL_ADL_S_GT1 0x4680 // RPL_S_6P_8E +#define PCI_DID_INTEL_ADL_S_GT1_1 0x4682 // RPL_S_4P_6E #define PCI_DID_INTEL_ADL_S_GT2 0x4690 -#define PCI_DID_INTEL_ADL_S_GT2_1 0x4692 +#define PCI_DID_INTEL_ADL_S_GT2_1 0x4692 // RPL_S_4P_0E #define PCI_DID_INTEL_ADL_S_GT2_2 0x4693 #define PCI_DID_INTEL_ADL_M_GT1 0x46c0 #define PCI_DID_INTEL_ADL_M_GT2 0x46aa @@ -4005,6 +4005,9 @@ #define PCI_DID_INTEL_MTL_P_GT2_2 0x7d50 #define PCI_DID_INTEL_MTL_P_GT2_3 0x7d55 #define PCI_DID_INTEL_MTL_P_GT2_4 0x7d60 +#define PCI_DID_INTEL_RPL_S_GT1 0xa780 +#define PCI_DID_INTEL_RPL_S_GT2 0xa782 +#define PCI_DID_INTEL_RPL_S_GT3 0xa783 #define PCI_DID_INTEL_RPL_P_GT1 0xa720 #define PCI_DID_INTEL_RPL_P_GT2 0xa7a8 #define PCI_DID_INTEL_RPL_P_GT3 0xa7a0 @@ -4102,9 +4105,9 @@ #define PCI_DID_INTEL_ADL_S_ID_3 0x4668 #define PCI_DID_INTEL_ADL_S_ID_4 0x466c #define PCI_DID_INTEL_ADL_S_ID_5 0x4670 -#define PCI_DID_INTEL_ADL_S_ID_6 0x4640 +#define PCI_DID_INTEL_ADL_S_ID_6 0x4640 // RPL_S_6P_8E #define PCI_DID_INTEL_ADL_S_ID_7 0x4644 -#define PCI_DID_INTEL_ADL_S_ID_8 0x4648 +#define PCI_DID_INTEL_ADL_S_ID_8 0x4648 // RPL_S_6P_4E #define PCI_DID_INTEL_ADL_S_ID_9 0x464c #define PCI_DID_INTEL_ADL_S_ID_10 0x4650 #define PCI_DID_INTEL_ADL_S_ID_11 0x4630 @@ -4132,6 +4135,11 @@ #define PCI_DID_INTEL_MTL_P_ID_2 0x7D02 #define PCI_DID_INTEL_MTL_P_ID_3 0x7d14 #define PCI_DID_INTEL_MTL_P_ID_4 0x7d15 +#define PCI_DID_INTEL_RPL_S_ID_1 0xa700 +#define PCI_DID_INTEL_RPL_S_ID_2 0xa703 +#define PCI_DID_INTEL_RPL_S_ID_3 0xa704 +#define PCI_DID_INTEL_RPL_S_ID_4 0xa705 +#define PCI_DID_INTEL_RPL_S_ID_5 0x4692 #define PCI_DID_INTEL_RPL_P_ID_1 0xa706 #define PCI_DID_INTEL_RPL_P_ID_2 0xa707 #define PCI_DID_INTEL_RPL_P_ID_3 0xa708 diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 08d4132..a09db54 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -154,7 +154,7 @@
config MAX_CPUS int - default 24 + default 32
config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/alderlake/Makefile.inc b/src/soc/intel/alderlake/Makefile.inc index 7f808ff..6f603b7 100644 --- a/src/soc/intel/alderlake/Makefile.inc +++ b/src/soc/intel/alderlake/Makefile.inc @@ -78,6 +78,7 @@ # 06-97-02 are ADL-S/HX Quality Samples but also ADL-HX Engineering Samples # ADL-S/HX C0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-02 +cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-b7-01 # ADL-S H0 cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-05 else diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 2be7546..e7d85b5 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -34,6 +34,7 @@ { CPUID_ALDERLAKE_S_C0, "Alderlake-S C0 Platform" }, { CPUID_ALDERLAKE_S_G0, "Alderlake-S G0 Platform" }, { CPUID_ALDERLAKE_S_H0, "Alderlake-S H0 Platform" }, + { CPUID_RAPTORLAKE_S_S0, "Raptorlake-S S0 Platform" }, { CPUID_RAPTORLAKE_P_J0, "Raptorlake-P J0 Platform" }, { CPUID_RAPTORLAKE_P_Q0, "Raptorlake-P Q0 Platform" }, }; @@ -71,6 +72,11 @@ { PCI_DID_INTEL_ADL_S_ID_12, "Alderlake-S (2+0)" }, { PCI_DID_INTEL_ADL_S_ID_13, "Alderlake-S" }, { PCI_DID_INTEL_ADL_S_ID_14, "Alderlake-S" }, + { PCI_DID_INTEL_RPL_S_ID_1, "Raptorlake-S (8+16)" }, + { PCI_DID_INTEL_RPL_S_ID_2, "Raptorlake-S (8+8)" }, + { PCI_DID_INTEL_RPL_S_ID_3, "Raptorlake-S (6+8)" }, + { PCI_DID_INTEL_RPL_S_ID_4, "Raptorlake-S (6+4)" }, + { PCI_DID_INTEL_RPL_S_ID_5, "Raptorlake-S (4+0)" }, { PCI_DID_INTEL_RPL_P_ID_1, "Raptorlake-P" }, { PCI_DID_INTEL_RPL_P_ID_2, "Raptorlake-P" }, { PCI_DID_INTEL_RPL_P_ID_3, "Raptorlake-P" }, @@ -198,6 +204,9 @@ { PCI_DID_INTEL_ADL_S_GT2, "Alderlake S GT2" }, { PCI_DID_INTEL_ADL_S_GT2_1, "Alderlake S GT2" }, { PCI_DID_INTEL_ADL_S_GT2_2, "Alderlake S GT2" }, + { PCI_DID_INTEL_RPL_S_GT1, "Raptorlake S GT1(32EU)" }, + { PCI_DID_INTEL_RPL_S_GT2, "Raptorlake S GT2(24EU)" }, + { PCI_DID_INTEL_RPL_S_GT3, "Raptorlake S GT3(16EU)" }, { PCI_DID_INTEL_RPL_P_GT1, "Raptorlake P GT1" }, { PCI_DID_INTEL_RPL_P_GT2, "Raptorlake P GT2" }, { PCI_DID_INTEL_RPL_P_GT3, "Raptorlake P GT3" }, diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index a732fe6..cdf47a1 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -132,6 +132,9 @@ { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_60W_CORE, TDP_60W }, { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_35W_CORE, TDP_35W }, { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_46W_CORE, TDP_46W }, + { PCI_DID_INTEL_RPL_S_ID_1, ADL_S_882_125W_CORE, TDP_125W }, + { PCI_DID_INTEL_RPL_S_ID_2, ADL_S_882_125W_CORE, TDP_125W }, + { PCI_DID_INTEL_RPL_S_ID_3, ADL_S_882_125W_CORE, TDP_125W }, { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W }, { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W }, { PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W }, diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 027e978..4ec1479 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -245,6 +245,14 @@ PCI_DID_INTEL_ADL_N_ID_4, };
+ const uint16_t rpl_s_mch_ids[] = { + PCI_DID_INTEL_RPL_S_ID_1, + PCI_DID_INTEL_RPL_S_ID_2, + PCI_DID_INTEL_RPL_S_ID_3, + PCI_DID_INTEL_RPL_S_ID_4, + PCI_DID_INTEL_RPL_S_ID_5 + }; + const uint16_t rpl_p_mch_ids[] = { PCI_DID_INTEL_RPL_P_ID_1, PCI_DID_INTEL_RPL_P_ID_2, @@ -271,6 +279,11 @@ return ADL_S; }
+ for (size_t i = 0; i < ARRAY_SIZE(rpl_s_mch_ids); i++) { + if (rpl_s_mch_ids[i] == mchid) + return RPL_S; + } + for (size_t i = 0; i < ARRAY_SIZE(adl_n_mch_ids); i++) { if (adl_n_mch_ids[i] == mchid) return ADL_N; @@ -294,6 +307,7 @@ case RPL_P: return LPM_S0i2_0 | LPM_S0i3_0; case ADL_S: + case RPL_S: return LPM_S0i2_0 | LPM_S0i2_1; default: printk(BIOS_ERR, "Unknown ADL CPU type: %d\n", type); diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 26eba76..1826be3 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -536,6 +536,11 @@ case PCI_DID_INTEL_ADL_S_ID_10: case PCI_DID_INTEL_ADL_S_ID_11: case PCI_DID_INTEL_ADL_S_ID_12: + case PCI_DID_INTEL_RPL_S_ID_1: + case PCI_DID_INTEL_RPL_S_ID_2: + case PCI_DID_INTEL_RPL_S_ID_3: + case PCI_DID_INTEL_RPL_S_ID_4: + case PCI_DID_INTEL_RPL_S_ID_5: return ICC_MAX_ADL_S; default: printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n", diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h index 424e02a..4cee4ae 100644 --- a/src/soc/intel/alderlake/include/soc/cpu.h +++ b/src/soc/intel/alderlake/include/soc/cpu.h @@ -25,6 +25,7 @@ ADL_N, ADL_P, ADL_S, + RPL_S, RPL_P, };
diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index c090641..080856a 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -126,6 +126,10 @@ { PCI_DID_INTEL_ADL_N_ID_2, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_ADL_N_ID_3, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, { PCI_DID_INTEL_ADL_N_ID_4, 6, VR_CFG_ALL_DOMAINS_LOADLINE(5.0, 6.5) }, + { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, + { PCI_DID_INTEL_RPL_S_ID_2, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, + { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, + { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, { PCI_DID_INTEL_RPL_P_ID_1, 45, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_LOADLINE(2.3, 3.2) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_LOADLINE(2.8, 3.2) }, @@ -167,6 +171,10 @@ { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_ICC(102, 55) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_ICC(80, 40) }, + { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, + { PCI_DID_INTEL_RPL_S_ID_2, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, + { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, + { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_ICC(280, 30) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_ICC(240, 30) }, @@ -204,6 +212,10 @@ { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC(28000, 28000) }, + { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_S_ID_2, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, @@ -241,6 +253,10 @@ { PCI_DID_INTEL_RPL_P_ID_2, 28, VR_CFG_ALL_DOMAINS_TDC_CURRENT(54, 54) }, { PCI_DID_INTEL_RPL_P_ID_3, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) }, { PCI_DID_INTEL_RPL_P_ID_4, 15, VR_CFG_ALL_DOMAINS_TDC_CURRENT(41, 41) }, + { PCI_DID_INTEL_RPL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, + { PCI_DID_INTEL_RPL_S_ID_2, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, + { PCI_DID_INTEL_RPL_S_ID_3, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, + { PCI_DID_INTEL_RPL_S_ID_4, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, { PCI_DID_INTEL_ADL_S_ID_1, 150, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, { PCI_DID_INTEL_ADL_S_ID_1, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(132, 132) }, { PCI_DID_INTEL_ADL_S_ID_1, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 89) }, diff --git a/src/soc/intel/common/block/cpu/mp_init.c b/src/soc/intel/common/block/cpu/mp_init.c index d8ca0b3..395ffa4 100644 --- a/src/soc/intel/common/block/cpu/mp_init.c +++ b/src/soc/intel/common/block/cpu/mp_init.c @@ -81,6 +81,7 @@ { X86_VENDOR_INTEL, CPUID_ALDERLAKE_Q0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_R0 }, { X86_VENDOR_INTEL, CPUID_ALDERLAKE_N_A0 }, + { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_S_S0 }, { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_P_J0 }, { X86_VENDOR_INTEL, CPUID_RAPTORLAKE_P_Q0 }, { 0, 0 }, diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 90b3335..aafdffb 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -439,6 +439,11 @@ PCI_DID_INTEL_ADL_N_ID_2, PCI_DID_INTEL_ADL_N_ID_3, PCI_DID_INTEL_ADL_N_ID_4, + PCI_DID_INTEL_RPL_S_ID_1, + PCI_DID_INTEL_RPL_S_ID_2, + PCI_DID_INTEL_RPL_S_ID_3, + PCI_DID_INTEL_RPL_S_ID_4, + PCI_DID_INTEL_RPL_S_ID_5, PCI_DID_INTEL_RPL_P_ID_1, PCI_DID_INTEL_RPL_P_ID_2, PCI_DID_INTEL_RPL_P_ID_3,