Attention is currently required from: Angel Pons, Evgeny Zinoviev, Alexander Couzens.
Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/70114 )
Change subject: sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary} ......................................................................
sb/intel/i82801gx: Use boolean for ide_enable_{primary,secondary}
Change-Id: Ia71692ecf74fd8921eeafabac9a4cb862da90e81 Signed-off-by: Elyes Haouas ehaouas@noos.fr --- M src/mainboard/apple/macbook21/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb M src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb M src/mainboard/asus/p5gc-mx/devicetree.cb M src/mainboard/asus/p5qpl-am/devicetree.cb M src/mainboard/foxconn/g41s-k/devicetree.cb M src/mainboard/getac/p470/devicetree.cb M src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb M src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb M src/mainboard/ibase/mb899/devicetree.cb M src/mainboard/intel/d945gclf/devicetree.cb M src/mainboard/intel/dg41wv/devicetree.cb M src/mainboard/kontron/986lcd-m/devicetree.cb M src/mainboard/lenovo/t60/mainboard.c M src/mainboard/lenovo/thinkcentre_a58/devicetree.cb M src/mainboard/lenovo/x60/mainboard.c M src/mainboard/roda/rk886ex/devicetree.cb M src/southbridge/intel/i82801gx/chip.h 21 files changed, 42 insertions(+), 32 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/14/70114/1
diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 322c129..acb2278 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -53,8 +53,8 @@ register "gpe0_en" = "0x11000006" register "alt_gp_smi_en" = "0x1000"
- register "ide_enable_primary" = "1" - register "ide_enable_secondary" = "1" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "true"
register "c3_latency" = "0x23"
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index ff050306..08df966 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -36,7 +36,7 @@ # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "2"
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440"
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index 89e6ebb..92b2a76 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -31,7 +31,7 @@ register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b"
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x440"
register "gen1_dec" = "0x000c0291" # Superio HWM diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index c3c6b1b..b9a839e 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -31,7 +31,7 @@ register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b"
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440"
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 9d22761..54a6296 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -29,7 +29,7 @@ register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b"
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440"
diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index 8693c01..728db85 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -31,7 +31,7 @@ register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x0b"
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x440"
register "gen1_dec" = "0x000c0291" # Superio HWM diff --git a/src/mainboard/asus/p5gc-mx/devicetree.cb b/src/mainboard/asus/p5gc-mx/devicetree.cb index 0737347..6bd1f5a 100644 --- a/src/mainboard/asus/p5gc-mx/devicetree.cb +++ b/src/mainboard/asus/p5gc-mx/devicetree.cb @@ -36,8 +36,8 @@
register "gpe0_en" = "0"
- register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false"
register "p_cnt_throttling_supported" = "false"
diff --git a/src/mainboard/asus/p5qpl-am/devicetree.cb b/src/mainboard/asus/p5qpl-am/devicetree.cb index 1cbee74..245a39ad 100644 --- a/src/mainboard/asus/p5qpl-am/devicetree.cb +++ b/src/mainboard/asus/p5qpl-am/devicetree.cb @@ -27,7 +27,7 @@ # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 2 SCI (if corresponding GPIO_EN bit is also set)
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x04000440"
register "gen1_dec" = "0x00000295" # HWM diff --git a/src/mainboard/foxconn/g41s-k/devicetree.cb b/src/mainboard/foxconn/g41s-k/devicetree.cb index 9bde4b2..8c24107 100644 --- a/src/mainboard/foxconn/g41s-k/devicetree.cb +++ b/src/mainboard/foxconn/g41s-k/devicetree.cb @@ -29,8 +29,8 @@ register "gpe0_en" = "0x00000441" register "alt_gp_smi_en" = "0x0000"
- register "ide_enable_primary" = "0x0" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "false" + register "ide_enable_secondary" = "false" register "sata_ports_implemented" = "0x3"
register "gen1_dec" = "0x003c0a01" # Super I/O EC and GPIO diff --git a/src/mainboard/getac/p470/devicetree.cb b/src/mainboard/getac/p470/devicetree.cb index 48784a1..6518a13 100644 --- a/src/mainboard/getac/p470/devicetree.cb +++ b/src/mainboard/getac/p470/devicetree.cb @@ -41,8 +41,8 @@ register "alt_gp_smi_en" = "0x0100"
register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false"
register "c3_latency" = "85"
diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb index 8c094a3..3a6c544 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/devicetree.cb @@ -59,8 +59,8 @@
register "gpe0_en" = "0"
- register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false" register "c3_latency" = "85"
register "p_cnt_throttling_supported" = "false" diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb index 6328bc6..d7d837f 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb +++ b/src/mainboard/gigabyte/ga-g41m-es2l/devicetree.cb @@ -30,8 +30,8 @@ register "pirqf_routing" = "0x0b" register "pirqg_routing" = "0x0b" register "pirqh_routing" = "0x0b" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false" register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x40"
diff --git a/src/mainboard/ibase/mb899/devicetree.cb b/src/mainboard/ibase/mb899/devicetree.cb index 1c64e85..619c0cb 100644 --- a/src/mainboard/ibase/mb899/devicetree.cb +++ b/src/mainboard/ibase/mb899/devicetree.cb @@ -32,8 +32,8 @@ # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1"
- register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false"
register "c3_latency" = "85" register "p_cnt_throttling_supported" = "false" diff --git a/src/mainboard/intel/d945gclf/devicetree.cb b/src/mainboard/intel/d945gclf/devicetree.cb index bcc6a26..76cad91 100644 --- a/src/mainboard/intel/d945gclf/devicetree.cb +++ b/src/mainboard/intel/d945gclf/devicetree.cb @@ -34,8 +34,8 @@ register "gpi13_routing" = "1" register "gpe0_en" = "0x20000601"
- register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "false"
diff --git a/src/mainboard/intel/dg41wv/devicetree.cb b/src/mainboard/intel/dg41wv/devicetree.cb index 5f945c1..11f1b54 100644 --- a/src/mainboard/intel/dg41wv/devicetree.cb +++ b/src/mainboard/intel/dg41wv/devicetree.cb @@ -48,7 +48,7 @@ register "gpi14_routing" = "2" register "gpi15_routing" = "2"
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x440"
register "gen1_dec" = "0x00fc0a01" # HWM diff --git a/src/mainboard/kontron/986lcd-m/devicetree.cb b/src/mainboard/kontron/986lcd-m/devicetree.cb index 0106bfe..98af6c6 100644 --- a/src/mainboard/kontron/986lcd-m/devicetree.cb +++ b/src/mainboard/kontron/986lcd-m/devicetree.cb @@ -33,8 +33,8 @@ register "gpi13_routing" = "1"
register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x1" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "true" register "c3_latency" = "85" register "p_cnt_throttling_supported" = "false"
diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 7ebe25e..5b38ec2 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -34,7 +34,7 @@ } else if (idedev && idedev->chip_info && h8_ultrabay_device_present()) { config = idedev->chip_info; - config->ide_enable_primary = 1; + config->ide_enable_primary = true; pmh7_ultrabay_power_enable(1); ec_write(0x0c, 0x84); } else { diff --git a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb index e5d10d7..6f50f83 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb +++ b/src/mainboard/lenovo/thinkcentre_a58/devicetree.cb @@ -29,7 +29,7 @@ # 2 SCI (if corresponding GPIO_EN bit is also set) register "gpi13_routing" = "1" # ??vendor
- register "ide_enable_primary" = "0x1" + register "ide_enable_primary" = "true" register "gpe0_en" = "0x440"
register "gen1_dec" = "0x00fc0a01" diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index 2eb0c38..238d949 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -37,7 +37,7 @@ idedev = pcidev_on_root(0x1f, 1); if (idedev && idedev->chip_info && dock_ultrabay_device_present()) { struct southbridge_intel_i82801gx_config *config = idedev->chip_info; - config->ide_enable_primary = 1; + config->ide_enable_primary = true; /* enable Ultrabay power */ outb(inb(0x1628) | 0x01, 0x1628); ec_write(0x0c, 0x84); diff --git a/src/mainboard/roda/rk886ex/devicetree.cb b/src/mainboard/roda/rk886ex/devicetree.cb index ae89783..e3a6db9 100644 --- a/src/mainboard/roda/rk886ex/devicetree.cb +++ b/src/mainboard/roda/rk886ex/devicetree.cb @@ -42,8 +42,8 @@ register "c3_latency" = "0x23"
register "sata_mode" = "SATA_MODE_IDE_LEGACY_COMBINED" - register "ide_enable_primary" = "0x1" - register "ide_enable_secondary" = "0x0" + register "ide_enable_primary" = "true" + register "ide_enable_secondary" = "false"
register "gen1_dec" = "0x001c02e1" # COM3, COM4 register "gen2_dec" = "0x00fc0601" # ?? diff --git a/src/southbridge/intel/i82801gx/chip.h b/src/southbridge/intel/i82801gx/chip.h index 18cfb71..b30e808 100644 --- a/src/southbridge/intel/i82801gx/chip.h +++ b/src/southbridge/intel/i82801gx/chip.h @@ -55,8 +55,8 @@ uint16_t alt_gp_smi_en;
/* IDE configuration */ - uint32_t ide_enable_primary; - uint32_t ide_enable_secondary; + bool ide_enable_primary; + bool ide_enable_secondary; enum sata_mode sata_mode; uint32_t sata_ports_implemented;