Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu.
Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85845?usp=email )
Change subject: soc/intel/xeon_sp: Add Xeon ICX-SP support ......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85845/comment/7d6a06c4_23d3e521?usp... : PS3, Line 9: Add support for the 1st Gen 10nm Xeon-SP CPUs. Supported and tested
ICX might be advertised as 3rd gen Xeon-SP, but this term is intentionally not used as CPX is also 3 […]
Technically yes but what I'm worried about is many users will refer to public URLs to check the products, e.g., https://www.intel.com/content/www/us/en/ark.html#@PanelLabel595, thus not straightforward to find a match.
Back to the previous discussion for SKX/CPX code merge, if we have both concept of ?? nm and ?? gen to co-exist, it would be helpful to be consistent with the meaning of 'gen' as the global generation instead of per 'nm' generation. This is adequate to distinguish CPX (14nm gen3) and ICX (10nm gen3), and as well as others.
Your opinion?
https://review.coreboot.org/c/coreboot/+/85845/comment/a60b94cd_dc91faa0?usp... : PS3, Line 10: are dual socket systems with a LBG PCH.
Yes. Mainboard support will be added as separate commit.
Done