[coreboot-gerrit] Change in coreboot[master]: sb/amd/sb700/bootblock.c: Separate IO decodes from ROM decoding

[Michał Żygowski (Code Review)]

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/62105 )

Change subject: sb/amd/sb700/bootblock.c: Separate IO decodes from ROM decoding
......................................................................

sb/amd/sb700/bootblock.c: Separate IO decodes from ROM decoding

Signed-off-by: Michał Żygowski 
Change-Id: I8dba6e563dc6ab57f1c7567ebfdadca6fd886c2b
---
M src/southbridge/amd/sb700/bootblock.c
1 file changed, 27 insertions(+), 21 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/62105/1

diff --git a/src/southbridge/amd/sb700/bootblock.c b/src/southbridge/amd/sb700/bootblock.c
index adc18d3..bacf7a8 100644
--- a/src/southbridge/amd/sb700/bootblock.c
+++ b/src/southbridge/amd/sb700/bootblock.c
@@ -72,27 +72,6 @@
    pci_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6));
    /* Enable LPC ROM range end at 0xffff(ffff). */
    pci_write_config16(dev, 0x6e, 0xffff);
-
-	/* SB700 LPC Bridge 0x48.
-	 * Turn on all LPC IO Port decode enables
-	 */
-	pci_write_config32(dev, 0x44, 0xffffffff);
-
-	/* SB700 LPC Bridge 0x48.
-	 * BIT0: Port Enable for SuperIO 0x2E-0x2F
-	 * BIT1: Port Enable for SuperIO 0x4E-0x4F
-	 * BIT6: Port Enable for RTC IO 0x70-0x73
-	 */
-	reg8 = pci_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
-	reg8 |= (1 << 0) | (1 << 1) | (1 << 6);
-	pci_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8);
-
-	/* SB700 LPC Bridge 0x4a.
-	 * BIT5: Port Enable for Port 0x80
-	 */
-	reg8 = pci_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6);
-	reg8 |= (1 << 5);
-	pci_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8);
 }

static void sb700_configure_rom(void)
@@ -123,8 +102,35 @@
    }
 }

+static void sb700_enable_io_decodes(void)
+{
+	u8 reg8;
+	pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
+	/* SB700 LPC Bridge 0x48.
+	 * Turn on all LPC IO Port decode enables
+	 */
+	pci_write_config32(dev, 0x44, 0xffffffff);
+
+	/* SB700 LPC Bridge 0x48.
+	 * BIT0: Port Enable for SuperIO 0x2E-0x2F
+	 * BIT1: Port Enable for SuperIO 0x4E-0x4F
+	 * BIT6: Port Enable for RTC IO 0x70-0x73
+	 */
+	reg8 = pci_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5);
+	reg8 |= (1 << 0) | (1 << 1) | (1 << 6);
+	pci_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_5, reg8);
+
+	/* SB700 LPC Bridge 0x4a.
+	 * BIT5: Port Enable for Port 0x80
+	 */
+	reg8 = pci_read_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6);
+	reg8 |= (1 << 5);
+	pci_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8);
+}
+
 void bootblock_early_southbridge_init(void)
 {
    sb700_enable_rom();
    sb700_configure_rom();
+	sb700_enable_io_decodes();
 }