[coreboot-gerrit] Change in coreboot[master]: google/link: fix detection of dimm on channel 1

[Matt DeVillier (Code Review)]

Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35084 )

Change subject: google/link: fix detection of dimm on channel 1
......................................................................

google/link: fix detection of dimm on channel 1

Changes to the sandybridge memory init code (both MRC
and native) now require SPD data on all populated channels
in order for dimms to be detected properly, so copy
spd_data[0] to spd_data[2], as LINK always has 2
channels of memory down.

Test: boot google/link, observe onboard RAM correctly
detected on both channels

Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe
Signed-off-by: Matt DeVillier 
---
M src/mainboard/google/link/romstage.c
1 file changed, 4 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/35084/1

diff --git a/src/mainboard/google/link/romstage.c b/src/mainboard/google/link/romstage.c
index 2f3f07c..1fe71ea 100644
--- a/src/mainboard/google/link/romstage.c
+++ b/src/mainboard/google/link/romstage.c
@@ -156,8 +156,12 @@
    	},
    };
    *pei_data = pei_data_template;
+	/* LINK has 2 channels of memory down, so spd_data[0] and [2]
+	   both need to be populated */
    memcpy(pei_data->spd_data[0], locate_spd(),
           sizeof(pei_data->spd_data[0]));
+	memcpy(pei_data->spd_data[2], pei_data->spd_data[0],
+	       sizeof(pei_data->spd_data[0]));
 }

const struct southbridge_usb_port mainboard_usb_ports[] = {