[coreboot-gerrit] Change in coreboot[master]: src/soc/tigerlake: Define and use config for number of USB2/3 ports.

[Meera Ravindranath (Code Review)]

Hello Patrick Rudolph, Aamir Bohra, build bot (Jenkins),

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/38682

to look at the new patch set (#3).

Change subject: src/soc/tigerlake: Define and use config for number of USB2/3 ports.
......................................................................

src/soc/tigerlake: Define and use config for number of USB2/3 ports.

Using a config for no of USB2/3 ports to be able to handle both tgl
and jsl in fsp params.

BUG=None
BRANCH=None
TEST=Compilation for jasper lake board is working

Change-Id: Ia8e88e92989fe40d7bd1c28942e005cb0d862fcb
Signed-off-by: Meera Ravindranath 
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/fsp_params_jsl.c
M src/soc/intel/tigerlake/fsp_params_tgl.c
3 files changed, 14 insertions(+), 4 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/38682/3