Thejaswani Putta has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35141 )
Change subject: mb/google/drallion: Add memory init setup for drallion ......................................................................
mb/google/drallion: Add memory init setup for drallion
This implementation adds below support 1. Add support to configure below memory parameters -> rcomp resistor configuration -> dqs mapping -> ect and ca vref config
Signed-off-by: Thejaswani Putta thejaswani.putta@intel.com Change-Id: I9993ad175e6f52711d5a05733aeab1bbed1e0b80 --- M src/mainboard/google/drallion/romstage.c M src/mainboard/google/drallion/variants/drallion/gpio.c M src/mainboard/google/drallion/variants/drallion/include/variant/variant.h M src/mainboard/google/drallion/variants/drallion/memory.c 4 files changed, 43 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/35141/1
diff --git a/src/mainboard/google/drallion/romstage.c b/src/mainboard/google/drallion/romstage.c index 20eee7f..fc5c7bd 100644 --- a/src/mainboard/google/drallion/romstage.c +++ b/src/mainboard/google/drallion/romstage.c @@ -57,6 +57,11 @@
void mainboard_memory_init_params(FSPM_UPD *memupd) { + const struct spd_info spd = { + .spd_by_index = true, + .spd_spec.spd_index = variant_memory_sku(), + }; + wilco_ec_romstage_init();
cannonlake_memcfg_init(&memupd->FspmConfig, &memcfg); diff --git a/src/mainboard/google/drallion/variants/drallion/gpio.c b/src/mainboard/google/drallion/variants/drallion/gpio.c index ff0240c..c20c6ff 100644 --- a/src/mainboard/google/drallion/variants/drallion/gpio.c +++ b/src/mainboard/google/drallion/variants/drallion/gpio.c @@ -234,6 +234,11 @@ /* SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */ /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */ /* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */ +/* PCH_MEM_STRAP0 */ PAD_CFG_GPI(GPP_F12, NONE, PLTRST), +/* PCH_MEM_STRAP1 */ PAD_CFG_GPI(GPP_F13, NONE, PLTRST), +/* PCH_MEM_STRAP2 */ PAD_CFG_GPI(GPP_F14, NONE, PLTRST), +/* PCH_MEM_STRAP3 */ PAD_CFG_GPI(GPP_F15, NONE, PLTRST), +/* PCH_MEM_STRAP4 */ PAD_CFG_GPI(GPP_F16, NONE, PLTRST), };
/* Early pad configuration in bootblock */ diff --git a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h index ca54580..51287d4 100644 --- a/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h +++ b/src/mainboard/google/drallion/variants/drallion/include/variant/variant.h @@ -25,4 +25,7 @@ /* Return memory SKU for the variant */ int variant_memory_sku(void);
-#endif +/* Return board specific memory configuration */ +const struct cnl_mb_cfg *variant_memory_params(void); + +#endif /* VARIANT_H */ diff --git a/src/mainboard/google/drallion/variants/drallion/memory.c b/src/mainboard/google/drallion/variants/drallion/memory.c index 2a1d8d9..25cab04 100644 --- a/src/mainboard/google/drallion/variants/drallion/memory.c +++ b/src/mainboard/google/drallion/variants/drallion/memory.c @@ -17,6 +17,35 @@ #include <gpio.h> #include <variant/gpio.h>
+static const struct cnl_mb_cfg baseboard_memcfg = { + /* + * The dqs_map arrays map the ddr4 pins to the SoC pins + * for both channels. + * + * the index = pin number on ddr4 part + * the value = pin number on SoC + */ + .dqs_map[DDR_CH0] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + .dqs_map[DDR_CH1] = { 0, 1, 4, 5, 2, 3, 6, 7 }, + + /* Baseboard uses 120, 81 and 100 rcomp resistors */ + .rcomp_resistor = { 120, 81, 100 }, + + /* Baseboard Rcomp target values */ + .rcomp_targets = { 100, 40, 20, 20, 26 }, + + /* Set CaVref config to 2 */ + .vref_ca_config = 2, + + /* Enable Early Command Training */ + .ect = 1, +}; + +const struct cnl_mb_cfg *__weak variant_memory_params(void) +{ + return &baseboard_memcfg; +} + int variant_memory_sku(void) { gpio_t spd_gpios[] = {