[coreboot-gerrit] [M] Change in coreboot[master]: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal para...

[Chris Wang (Code Review)]

Attention is currently required from: Jason Glenesk, Raul Rangel, Jason Nien, EricKY Cheng, Matt DeVillier, Martin Roth, Tim Van Patten, Fred Reitberger, Felix Held.

Chris Wang has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/68649 )

Change subject: soc/amd/mendocino: Enhance DPTC_INPUT to support 13 DPTC thermal parameters
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Patch Set 31:

(1 comment)

File src/soc/amd/mendocino/root_complex.c:

https://review.coreboot.org/c/coreboot/+/68649/comment/a8e850d7_9382d3cb 
PS16, Line 393: #else
> My concern is that the new fields added to `DPTC_INPUTS()` need to be added to `google/skyrim/varian […]

for below settings
vrm_current_limit_throttle_mA,
vrm_maximum_current_limit_throttle_mA,
vrm_soc_current_limit_throttle_mA,

since the below settings will apply to dptc parameters, it's better to follow AMD IRM, or you have your own setting that needs to apply to.
There's no other STT setting that will be changed via DPTC, so those values will keep the value you set to default in devtree.