[coreboot-gerrit] Change in coreboot[master]: intel/i945,i82801gx: Refactor early PCI bridge reset

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/35678 )

Change subject: intel/i945,i82801gx: Refactor early PCI bridge reset
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Patch Set 2:

(1 comment)

https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... 
File src/northbridge/intel/i945/early_init.c:

https://review.coreboot.org/c/coreboot/+/35678/1/src/northbridge/intel/i945/... 
PS1, Line 876: mdelay(200);
> If there is a PCI(e/-X) specification requirement for an assertion to have some duration. […]

I only found 1ms Trst for RST# assertion in the specs.

I am pretty sure this 200ms was discussed once before, maybe in relation to some exotic add-on PCI hardware? It might be just a delay in general, RST# asserted or not, that was required.

commit bc8613ec