Attention is currently required from: Tarun Tuli, Subrata Banik.
Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69950 )
Change subject: soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden ......................................................................
soc/intel/alderlake/{chipset.cb,chipset_pch_s.cb}: Set P2SB as hidden
Set the P2SB device as hidden as FSP-S is hiding the PCI configuration space from coreboot on Alder Lake systems.
Signed-off-by: Michał Żygowski michal.zygowski@3mdeb.com Change-Id: I5cfde7c1f6791578a03d73e89bcde31af608f12d --- M src/soc/intel/alderlake/chipset.cb M src/soc/intel/alderlake/chipset_pch_s.cb 2 files changed, 15 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/50/69950/1
diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb index 09dc970..86514047 100644 --- a/src/soc/intel/alderlake/chipset.cb +++ b/src/soc/intel/alderlake/chipset.cb @@ -204,7 +204,7 @@ device pci 1e.2 alias gspi0 off end device pci 1e.3 alias gspi1 off end device pci 1f.0 alias pch_espi on end - device pci 1f.1 alias p2sb off end + device pci 1f.1 alias p2sb hidden end device pci 1f.2 alias pmc hidden end device pci 1f.3 alias hda off end device pci 1f.4 alias smbus off end diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb index 2ade381..8effd21 100644 --- a/src/soc/intel/alderlake/chipset_pch_s.cb +++ b/src/soc/intel/alderlake/chipset_pch_s.cb @@ -206,7 +206,7 @@ device pci 1e.2 alias gspi0 off end device pci 1e.3 alias gspi1 off end device pci 1f.0 alias pch_espi on end - device pci 1f.1 alias p2sb off end + device pci 1f.1 alias p2sb hidden end device pci 1f.2 alias pmc hidden end device pci 1f.3 alias hda off end device pci 1f.4 alias smbus off end