Hello Nicolas Boichat,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/46385
to review the following change.
Change subject: HACK: mt8192: Add SPI support ......................................................................
HACK: mt8192: Add SPI support
Missing pinctrl, so we just hardcode SPI1/SPI5 pins for now.
TODO: There's actually 8 SPI controllers, I think
BUG=none TEST=boot asurada
Change-Id: I0f169407d1726899fd0c42e144d907024f036c6a --- M src/mainboard/google/asurada/Kconfig M src/mainboard/google/asurada/bootblock.c 2 files changed, 6 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/46385/1
diff --git a/src/mainboard/google/asurada/Kconfig b/src/mainboard/google/asurada/Kconfig index 894d566..7c93815 100644 --- a/src/mainboard/google/asurada/Kconfig +++ b/src/mainboard/google/asurada/Kconfig @@ -39,7 +39,7 @@
config DRIVER_TPM_SPI_BUS hex - default 0x0 + default 0x5
# On MT8192 the SPI flash is actually using a SPI-NOR controller with its own bus. # The number here should be a virtual value as (SPI_BUS_NUMBER + 1). @@ -49,6 +49,6 @@
config EC_GOOGLE_CHROMEEC_SPI_BUS hex - default 0x2 + default 0x1
endif diff --git a/src/mainboard/google/asurada/bootblock.c b/src/mainboard/google/asurada/bootblock.c index 5dcae8c..3eb05e1 100644 --- a/src/mainboard/google/asurada/bootblock.c +++ b/src/mainboard/google/asurada/bootblock.c @@ -1,7 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */
#include <bootblock_common.h> +#include <soc/spi.h>
void bootblock_mainboard_init(void) { + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); + mtk_spi_init(CONFIG_DRIVER_TPM_SPI_BUS, SPI_PAD0_MASK, 1 * MHz, 0); + //gpio_eint_configure(CR50_IRQ, IRQ_TYPE_EDGE_RISING); }