Hello Felix Singer, Nico Huber, Arthur Heymans, Patrick Rudolph,
I'd like you to do a code review. Please visit
https://review.coreboot.org/c/coreboot/+/48413
to review the following change.
Change subject: nb/intel/sandybridge: Only run DMI recipe on Ivy Bridge ......................................................................
nb/intel/sandybridge: Only run DMI recipe on Ivy Bridge
Reference code does not run the DMI recipe for Sandy Bridge.
Change-Id: I5d7afb1ef516f447b4988dd5c2f0295771d5888e Signed-off-by: Angel Pons th3fanbus@gmail.com --- M src/northbridge/intel/sandybridge/early_dmi.c 1 file changed, 25 insertions(+), 17 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/48413/1
diff --git a/src/northbridge/intel/sandybridge/early_dmi.c b/src/northbridge/intel/sandybridge/early_dmi.c index e41cc87..5a0f098 100644 --- a/src/northbridge/intel/sandybridge/early_dmi.c +++ b/src/northbridge/intel/sandybridge/early_dmi.c @@ -25,17 +25,19 @@ DMIBAR32(0x91c + 0x20 * (lane >> 1)) = lbcvalue; }
-void early_init_dmi(void) +static void dmi_recipe(const u32 cpuid) { - const u32 cpuid = cpu_get_cpuid(); - const u8 stepping = cpuid & 0xf;
u32 value; int i;
+ /* DMI recipe is only valid for Ivy Bridge */ + if (!IS_IVY_CPU(cpuid)) + return; + /* E1 PWRFSM fix */ - if (IS_IVY_CPU(cpuid) && stepping == IVB_STEP_E1) { + if (stepping == IVB_STEP_E1) { for (i = 0; i < 2; i++) dmi_update_field(0x0914 + (i << 5), 1, 1, 31); } @@ -69,7 +71,7 @@ for (i = 0; i < 2; i++) dmi_update_field(0x090c + (i << 5), 0xf, value, 21);
- if (IS_IVY_CPU(cpuid) && stepping <= IVB_STEP_B0) { + if (stepping <= IVB_STEP_B0) {
/* setrxincmval */ dmi_update_field(0x0c08, 0x3f, 8, 4); @@ -88,7 +90,7 @@ }
/* setl0sfixes */ - if (IS_IVY_CPU(cpuid) && stepping >= IVB_STEP_C0) { + if (stepping >= IVB_STEP_C0) { for (i = 0; i < 2; i++) dmi_update_field(0x0700 + (i << 5), 1, 1, 15); } @@ -109,15 +111,15 @@ dmi_update_field(0x0a00 + (i << 4), 0x1f, 12, 1);
/* setbypscmcode */ - value = IS_IVY_CPU(cpuid) && stepping >= IVB_STEP_C0 ? 0 : 1; + value = stepping >= IVB_STEP_C0 ? 0 : 1; dmi_update_field(0x0c00, 1, value, 4);
/* setctleoc */ - value = IS_IVY_CPU(cpuid) && stepping >= IVB_STEP_C0 ? 1 : 0; + value = stepping >= IVB_STEP_C0 ? 1 : 0; for (i = 0; i < 4; i++) dmi_update_field(0x0a04 + (i << 4), 1, value, 12);
- if (IS_IVY_CPU(cpuid) && stepping >= IVB_STEP_C0) { + if (stepping >= IVB_STEP_C0) { /* setdfelsbsel */ for (i = 0; i < 2; i++) dmi_update_field(0x0900 + (i << 5), 3, 0, 26); @@ -148,7 +150,7 @@ dmi_update_field(0x0908 + (i << 5), 3, 1, 30);
/* Swing Control: Reduced */ - if (IS_IVY_CPU(cpuid) && stepping >= IVB_STEP_C0) { + if (stepping >= IVB_STEP_C0) { /* setpegvcm */ dmi_update_field(0x0c00, 0x1f, 0x14, 25);
@@ -156,7 +158,7 @@ dmi_update_field(0x0c0c, 0x1f, 0x00, 23); }
- if (IS_IVY_CPU(cpuid) && stepping >= IVB_STEP_K0) { + if (stepping >= IVB_STEP_K0) { /* setK0ctocfix */ for (i = 0; i < 2; i++) dmi_update_field(0x0700 + (i << 5), 1, 1, 21); @@ -179,7 +181,7 @@ }
/* setctleocgen2 */ - if (IS_IVY_CPU(cpuid) && stepping >= IVB_STEP_D0) { + if (stepping >= IVB_STEP_D0) { for (i = 0; i < 2; i++) dmi_update_field(0x0914 + (i << 5), 1, 1, 9); } @@ -188,29 +190,28 @@ * ECO(3621419): Aggresive Rx L0s freeze resulting in Rx * errors since AGC is in open loop for long time (L0s Exit) */ - if (IS_IVY_CPU(cpuid) && stepping >= IVB_STEP_E0) { + if (stepping >= IVB_STEP_E0) { for (i = 0; i < 2; i++) dmi_update_field(0x0914 + (i << 5), 1, 1, 27); }
/* setD0disableL1exitfix */ - if (IS_IVY_CPU(cpuid) && stepping == IVB_STEP_D0) + if (stepping == IVB_STEP_D0) dmi_update_field(0x0c38, 1, 1, 27);
/* * afeln0cfg0_d1f0.useerrd * FIXME: PEG only */ - if (IS_IVY_CPU(cpuid) && stepping >= IVB_STEP_D0) { + if (stepping >= IVB_STEP_D0) { for (i = 0; i < 4; i++) dmi_update_field(0x0a00 + (i << 4), 1, 1, 21); - }
/* DMIBAR D0 */ dmi_update_field(0x0258, 1, 1, 29);
- if (IS_IVY_CPU(cpuid) && stepping >= IVB_STEP_D0) { + if (stepping >= IVB_STEP_D0) { for (i = 0; i < 2; i++) { /* setD0dfeidacpdgen1 */ dmi_update_field(0x0904 + (i << 5), 0xf, 5, 25); @@ -222,6 +223,13 @@
/* Update the N_FTS values */ dmi_update_field(DMIL0SLAT, 0xffff, 0x403c, 0); +} + +void early_init_dmi(void) +{ + const u32 cpuid = cpu_get_cpuid(); + + dmi_recipe(cpuid);
early_pch_init_native_dmi_pre();