Michael Niewöhner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/45571 )
Change subject: soc/intel/alderlake: Add GPIOs for Alder Lake SOC ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... File src/soc/intel/alderlake/include/soc/gpio_soc_defs.h:
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 187: GPD_INPUT3VSEL 132 : #define GPD_SLP_LANB 133 : #define GPD__SLP_SUSB 134
I doubt CNL is a good example on how to do things. […]
right, we *had* a problem; it's merged...
ACK on consitency between all platforms
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 302: #define GPP_SPI_MOSI_IO_0 227 : #define GPP_SPI_MOSI_IO_1 22
I don't think the proposed renaming is a good idea. […]
The names _MOSI_ are wrong in EDS and FSP already, where those names come from. I would name the pins like they are named in PCH ds and (later) in (RVP) schematics.
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 305: PI_FLASH_0_CSB 230 : #define GPP_SPI_FLASH_1_CSB
`CSx` makes it harder to differentiate the macros. Having the numbers separated eases distinction. […]
Same as above; yes, it makes it harder to differentiate, however, I'd keep the "real" names of the pins here
https://review.coreboot.org/c/coreboot/+/45571/2/src/soc/intel/alderlake/inc... PS2, Line 309:
I think we would want to configure some of these GPIOs someday. But since ADL is not released yet, I don't mind if the definitions get added once it is.
ACK
Michael: I can't see Azalia in the GPIO group list, but looks like these pins exist in the CPU group.
Depends, have a look at CNL in Linux and coreboot. HDACPU pins are in the CPU group, while AZALIA is a group on its own.
Also, I imagine the kernel doesn't have definitions for ADL GPIOs because ADL is not released yet.
Yeah, I think so, too