[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Change SA_PCIEX_LENGTH to 256MB

[Arthur Heymans (Code Review)]

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37704 )

Change subject: soc/intel/skylake: Change SA_PCIEX_LENGTH to 256MB
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Patch Set 1:

The number of busses is typically configurable in PCI configuration, which afaik is done by FSP. ACPI has to match the hardware configuration, so the commit message should say if that is the case and how it was tested/verified.