Marc Jones (marc.jones@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7996
-gerrit
commit f625bd91aeb8b533bb2dbcce9c68d53127e9fe2f Author: Vadim Bendebury vbendeb@chromium.org Date: Thu May 1 14:45:56 2014 -0700
ipq8064: add dynamic CBMEM support
All what's needed apart from configuring the feature is to provide a function which would report the top of DRAM address.
BUG=chrome-os-partner:27784 TEST=manual . with all other patches applied, the image proceeds all the way to trying to download 'fallback/payload'.
Original-Signed-off-by: Vadim Bendebury vbendeb@chromium.org Original-Change-Id: Ifa586964c931976df1dff354066670463f8e9ee3 Original-Reviewed-on: https://chromium-review.googlesource.com/197897 (cherry picked from commit 54fed275fe80dee66d423ddd78a071d3f063464a) Signed-off-by: Marc Jones marc.jones@se-eng.com
Change-Id: I45f7016dd510fe0e924b63eb85da607c1652af74 --- src/mainboard/google/storm/Kconfig | 2 +- src/soc/qualcomm/ipq806x/Kconfig | 1 + src/soc/qualcomm/ipq806x/Makefile.inc | 1 + src/soc/qualcomm/ipq806x/cbmem.c | 25 +++++++++++++++++++++++++ 4 files changed, 28 insertions(+), 1 deletion(-)
diff --git a/src/mainboard/google/storm/Kconfig b/src/mainboard/google/storm/Kconfig index 3f7cbd6..4c90c4e 100644 --- a/src/mainboard/google/storm/Kconfig +++ b/src/mainboard/google/storm/Kconfig @@ -38,6 +38,6 @@ config MAINBOARD_PART_NUMBER
config DRAM_SIZE_MB int - default 2048 + default 512
endif # BOARD_GOOGLE_STORM diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 8ca6df9..12f31c7 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -6,6 +6,7 @@ config SOC_QC_IPQ806X select ARCH_RAMSTAGE_ARMV7 select ARM_LPAE select BOOTBLOCK_CONSOLE + select DYNAMIC_CBMEM select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING
diff --git a/src/soc/qualcomm/ipq806x/Makefile.inc b/src/soc/qualcomm/ipq806x/Makefile.inc index 94c7cb9..2379d63 100644 --- a/src/soc/qualcomm/ipq806x/Makefile.inc +++ b/src/soc/qualcomm/ipq806x/Makefile.inc @@ -30,6 +30,7 @@ romstage-$(CONFIG_SPI_FLASH) += spi.c romstage-y += timer.c romstage-$(CONFIG_DRIVERS_UART) += uart.c
+ramstage-y += cbmem.c ramstage-y += clock.c ramstage-y += gpio.c ramstage-$(CONFIG_SPI_FLASH) += spi.c diff --git a/src/soc/qualcomm/ipq806x/cbmem.c b/src/soc/qualcomm/ipq806x/cbmem.c new file mode 100644 index 0000000..b175d6a --- /dev/null +++ b/src/soc/qualcomm/ipq806x/cbmem.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <cbmem.h> + +void *cbmem_top(void) +{ + return (void *)(CONFIG_SYS_SDRAM_BASE + (CONFIG_DRAM_SIZE_MB << 20)); +}