[coreboot-gerrit] Change in coreboot[master]: soc/amd/picasso: Enable cache in bootblock

[Marshall Dawson (Code Review)]

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/38691 )

Change subject: soc/amd/picasso: Enable cache in bootblock
......................................................................

soc/amd/picasso: Enable cache in bootblock

Unlike prior AMD programs, picasso cannot rely on the cache-as- RAM
setup code to properly enable MTRRs.  Add that capabability to the
bootblock_c_entry() function.  In addition, enable an MTRR to cache
(WP) the flash boot device and another for WB of the non-XIP bootblock
running in DRAM.

Change-Id: I5615ff60ca196e622a939b46276a4a0940076ebe
Signed-off-by: Marshall Dawson 
---
M src/soc/amd/picasso/bootblock/bootblock.c
1 file changed, 56 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/38691/1

diff --git a/src/soc/amd/picasso/bootblock/bootblock.c b/src/soc/amd/picasso/bootblock/bootblock.c
index 1d3a98f..00f8416 100644
--- a/src/soc/amd/picasso/bootblock/bootblock.c
+++ b/src/soc/amd/picasso/bootblock/bootblock.c
@@ -12,10 +12,14 @@
  */

#include <stdint.h>
+#include <symbols.h>
 #include <bootblock_common.h>
 #include <console/console.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/msr.h>
 #include <cpu/amd/msr.h>
 #include <cpu/x86/mtrr.h>
+#include <cpu/amd/mtrr.h>
 #include <timestamp.h>
 #include <soc/southbridge.h>
 #include <soc/i2c.h>
@@ -31,10 +35,62 @@
    wrmsr(MMIO_CONF_BASE, mmconf);
 }

+static const unsigned int fixed_mtrrs[] = {
+	MTRR_FIX_64K_00000,
+	MTRR_FIX_16K_80000,
+	MTRR_FIX_16K_A0000,
+	MTRR_FIX_4K_C0000,
+	MTRR_FIX_4K_C8000,
+	MTRR_FIX_4K_D0000,
+	MTRR_FIX_4K_D8000,
+	MTRR_FIX_4K_E0000,
+	MTRR_FIX_4K_E8000,
+	MTRR_FIX_4K_F0000,
+	MTRR_FIX_4K_F8000,
+};
+
+static void set_caching(void)
+{
+	msr_t deftype, syscfg, rwmem;
+	int mtrr;
+	int i;
+
+	syscfg = rdmsr(SYSCFG_MSR);
+	syscfg.lo |= SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn
+				| SYSCFG_MSR_MtrrVarDramEn;
+	wrmsr(SYSCFG_MSR, syscfg);
+
+	/* Write all as MTRR_READ_MEM | MTRR_WRITE_MEM to send 0-1M cycles to DRAM */
+	rwmem.hi = rwmem.lo = 0x18181818;
+	for (i = 0 ; i < ARRAY_SIZE(fixed_mtrrs) ; i++)
+		wrmsr(fixed_mtrrs[i], rwmem);
+
+	syscfg.lo &= ~(SYSCFG_MSR_MtrrFixDramModEn | SYSCFG_MSR_MtrrFixDramEn);
+	wrmsr(SYSCFG_MSR, syscfg);
+
+	deftype = rdmsr(MTRR_DEF_TYPE_MSR);
+	deftype.lo &= ~MTRR_DEF_TYPE_MASK;
+	deftype.lo |= MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN | MTRR_TYPE_UNCACHEABLE;
+	wrmsr(MTRR_DEF_TYPE_MSR, deftype);
+
+	mtrr = get_free_var_mtrr();
+	if (mtrr < 0)
+		return;
+	set_var_mtrr(mtrr, FLASH_BASE_ADDR, CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT);
+
+	mtrr = get_free_var_mtrr();
+	if (mtrr < 0)
+		return;
+	set_var_mtrr(mtrr, (unsigned int)_bootblock, _ebootblock - _bootblock, MTRR_TYPE_WRBACK);
+
+	enable_cache();
+}
+
 asmlinkage void bootblock_c_entry(uint64_t base_timestamp)
 {
    enable_pci_mmconf();
    amd_initmmio();
+	set_caching();

bootblock_main_with_basetime(base_timestamp);
 }